Honglan Jiang

Orcid: 0000-0003-3705-4240

According to our database1, Honglan Jiang authored at least 37 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Online presence:

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Bibliography

2024
Learning the Error Features of Approximate Multipliers for Neural Network Applications.
IEEE Trans. Computers, March, 2024

Hardware-Efficient Logarithmic Floating-Point Multipliers for Error-Tolerant Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2024

An Architectural Error Metric for CNN-Oriented Approximate Multipliers.
CoRR, 2024

A Low-Power and High-Accuracy Approximate Adder for Logarithmic Number System.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

A Configurable Approximate Multiplier for CNNs Using Partial Product Speculation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Compact Powers-of-Two: An Efficient Non-Uniform Quantization for Deep Neural Networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

QUQ: Quadruplet Uniform Quantization for Efficient Vision Transformer Inference.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023
Approximate Processing Element Design and Analysis for the Implementation of CNN Accelerators.
J. Comput. Sci. Technol., April, 2023

Feature-Embedding Triplet Networks with a Separately Constrained Loss Function.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

COSA:Co-Operative Systolic Arrays for Multi-head Attention Mechanism in Neural Network using Hybrid Data Reuse and Fusion Methodologies.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
An Energy-Efficient Approximate Divider Based on Logarithmic Conversion and Piecewise Constant Approximation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Characterizing Approximate Adders and Multipliers for Mitigating Aging and Temperature Degradations.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

HSB-GDM: a Hybrid Stochastic-Binary Circuit for Gradient Descent with Momentum in the Training of Neural Networks.
Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, 2022

Upward Packet Popup for Deadlock Freedom in Modular Chiplet-Based Systems.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

Majority Logic-Based Approximate Multipliers for Error-Tolerant Applications.
Proceedings of the Approximate Computing, 2022

2021
Non-Volatile Approximate Arithmetic Circuits Using Scalable Hybrid Spin-CMOS Majority Gates.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A Logarithmic Floating-Point Multiplier for the Efficient Training of Neural Networks.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

2020
Approximate Arithmetic Circuits: A Survey, Characterization, and Recent Applications.
Proc. IEEE, 2020

Interplay Bitwise Operation in Emerging MRAM for Efficient In-memory Computing.
CCF Trans. High Perform. Comput., 2020

Power-Efficient Approximate Multiplier Using Adaptive Error Compensation.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

2019
Low-Power Approximate Unsigned Multipliers With Configurable Error Recovery.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A High-Performance and Energy-Efficient FIR Adaptive Filter Using Approximate Distributed Arithmetic Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Low-Power Unsigned Divider and Square Root Circuit Designs Using Adaptive Approximation.
IEEE Trans. Computers, 2019

Pj-AxMTJ: Process-in-memory with Joint Magnetization Switching for Approximate Computing in Magnetic Tunnel Junction.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Characterizing Approximate Adders and Multipliers Optimized under Different Design Constraints.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Approximate Arithmetic Circuits: Design and Evaluation.
Proceedings of the Approximate Circuits, Methodologies and CAD., 2019

2018
Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Gradient Descent Using Stochastic Circuits for Efficient Training of Learning Machines.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Low-Power Approximate Multipliers Using Encoded Partial Products and Approximate Compressors.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Adaptive approximation in arithmetic circuits: A low-power unsigned divider design.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing.
IEEE Trans. Computers, 2017

A Review, Classification, and Comparative Evaluation of Approximate Arithmetic Circuits.
ACM J. Emerg. Technol. Comput. Syst., 2017

An efficient hardware design for cerebellar models using approximate circuits: special session paper.
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017

2016
Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation.
IEEE Trans. Computers, 2016

A comparative evaluation of approximate multipliers.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Adaptive Filter Design Using Stochastic Circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

2015
A Comparative Review and Evaluation of Approximate Adders.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015


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