Honghui Deng
Orcid: 0000-0002-5549-623X
According to our database1,
Honghui Deng
authored at least 21 papers
between 2008 and 2025.
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Bibliography
2025
Digital background calibration algorithm for pipelined ADC based on time-delay neural network with genetic algorithm feature selection.
Integr., 2025
2024
Microelectron. J., 2024
2023
Inf. Technol. Manag., December, 2023
IEICE Trans. Electron., March, 2023
2022
Microelectron. J., 2022
A Low-latency Multi-format Carrier Phase Recovery Hardware for Coherent Optical Communication.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
2021
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
2020
An efficient background calibration technique for analog-to-digital converters based on neural network.
Integr., 2020
A split-based fully digital feedforward background calibration technique for timing mismatch in TIADC.
Integr., 2020
Calibration of timing mismatch in TIADC based on monotonicity detecting of sampled data.
IEICE Electron. Express, 2020
2019
A channel multiplexing digital calibration technique for timing mismatch of time-interleaved ADCs.
IEICE Electron. Express, 2019
2017
Single event double-upset fully immune and transient pulse filterable latch design for nanoscale CMOS.
Microelectron. J., 2017
The impact of retailers' alliance on manufacturer's profit in a dual-channel structure.
Int. J. Prod. Res., 2017
2016
A Low Complexity All-Digital Background Calibration Technique for Time-Interleaved ADCs.
VLSI Design, 2016
2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2013
DEA analysis of FDI attractiveness for sustainable development: Evidence from Chinese provinces.
Decis. Support Syst., 2013
2011
The Use of Switching Point and Protection Levels to Improve Revenue Performance in Order-Driven Production Systems.
Decis. Sci., 2011
2008
Decis. Sci., 2008
A 14-bit 320 MSPS Segmented Current-Steering D/A Converter for High-Speed Applications.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008
A low power consumption, high speed Op-amp for a 10-bit 100MSPS parallel pipeline ADC.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008