Hongbing Pan

Orcid: 0000-0002-7181-8278

According to our database1, Hongbing Pan authored at least 42 papers between 2010 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2024
ONNXPruner: ONNX-Based General Model Pruning Adapter.
CoRR, 2024

2023
TEA-S: A Tiny and Efficient Architecture for PLAC-Based Softmax in Transformers.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2023

SHINE: protein language model-based pathogenicity prediction for short inframe insertion and deletion variants.
Briefings Bioinform., January, 2023

2022
TEA-Z: A Tiny and Efficient Architecture Based on Z Channel for Image Watermarking and Its Versatile Hardware Implementation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

A New Design of a CMOS Vertical Hall Sensor with a Low Offset.
Sensors, 2022

An optimized hardware implementation of the CORDIC algorithm.
IEICE Electron. Express, 2022

2021
CLA Formula and its Acceleration of Architecture Design for Clustered Look-Ahead Pipelined Recursive Digital Filter.
J. Signal Process. Syst., 2021

Ultralow-Latency VLSI Architecture Based on a Linear Approximation Method for Computing Nth Roots of Floating-Point Numbers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Effective Plug-Ins for Reducing Inference-Latency of Spiking Convolutional Neural Networks During Inference Phase.
Frontiers Comput. Neurosci., 2021

2020
GH CORDIC-Based Architecture for Computing $N$ th Root of Single-Precision Floating-Point Number.
IEEE Trans. Very Large Scale Integr. Syst., 2020

PLAC: Piecewise Linear Approximation Computation for All Nonlinear Unary Functions.
IEEE Trans. Very Large Scale Integr. Syst., 2020

A Universal Method of Linear Approximation With Controllable Error for the Efficient Implementation of Transcendental Functions.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A Novel Approximation Methodology and Its Efficient VLSI Implementation for the Sigmoid Function.
IEEE Trans. Circuits Syst., 2020

A low-power 2.4-GHz receiver front-end with a complementary series feedback LNA and a current-reused passive down-converter based on gm-boosted TIA for WSN applications.
IEICE Electron. Express, 2020

A Universal Approximation Method and Optimized Hardware Architectures for Arithmetic Functions Based on Stochastic Computing.
IEEE Access, 2020

An Optimized Compression Strategy for Compressor-Based Approximate Multiplier.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Corrections to "Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base".
IEEE Trans. Very Large Scale Integr. Syst., 2019

Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Thermal Sensor Placement and Thermal Reconstruction Under Gaussian and Non-Gaussian Sensor Noises for 3-D NoC.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

CLA Formula Aided Fast Architecture Design for Clustered Look-Ahead Pipelined IIR Digital Filter.
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

2018
CORDIC-Based Architecture for Computing Nth Root and Its Implementation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A New Design of a Single-Device 3D Hall Sensor: Cross-Shaped 3D Hall Sensor.
Sensors, 2018

2017
An access pattern based adaptive mapping function for GPGPU scratchpad memory.
IEICE Electron. Express, 2017

Application space exploration of a multi-fabric reconfigurable system.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
Influences of an Aluminum Covering Layer on the Performance of Cross-Like Hall Devices.
Sensors, 2016

An ultra-long FFT architecture implemented in a reconfigurable application specified processor.
IEICE Electron. Express, 2016

Accurate runtime thermal prediction scheme for 3D NoC systems with noisy thermal sensors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Performance Comparison of Cross-Like Hall Plates with Different Covering Layers.
Sensors, 2015

Exploring stacked main memory architecture for 3D GPGPUs.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

An improved FFT architecture optimized for reconfigurable application specified processor.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Lateral asynchronous and vertical synchronous 3D Network on Chip with double pumped vertical links.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A high performance parallel VLSI design of matrix inversion.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
A survey of memory architecture for 3D chip multi-processors.
Microprocess. Microsystems, 2014

A more accurate circuit model for CMOS Hall cross with non-linear resistors and JFETs.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

2013
Monolithic H-bridge brushless DC vibration motor driver with a highly sensitive hall sensor in 0.18 μm complementary metal-oxide semiconductor technology.
IET Circuits Devices Syst., 2013

Mass message transmission aware buffer-less packet-circuit switching router for 3D NoC.
Proceedings of the 10th IEEE International Conference on Control and Automation, 2013

Performance and power consumption analysis of memory efficient 3D network-on-chip architecture.
Proceedings of the 10th IEEE International Conference on Control and Automation, 2013

2012
Unified Architecture for Reed-Solomon Decoder Combined With Burst-Error Correction.
IEEE Trans. Very Large Scale Integr. Syst., 2012

A Highly Sensitive CMOS Digital Hall Sensor for Low Magnetic Field Applications.
Sensors, 2012

2011
An Improved Equivalent Simulation Model for CMOS Integrated Hall Plates.
Sensors, 2011

Latency-aware mapping for 3D NoC using rank-based multi-objective genetic algorithm.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
Application-level pipelining on Hierarchical NoC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010


  Loading...