Hong-Yi Huang

According to our database1, Hong-Yi Huang authored at least 79 papers between 1993 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
A 12-Phase and 5-GHz PLL with a Subfeedback Loop Technique.
Circuits Syst. Signal Process., April, 2023

Buck Converter with Variable Output Voltage for Dynamic Voltage Scaling (DVS) Applications.
Proceedings of the 22nd International Symposium on Communications and Information Technologies, 2023

RF Energy Harvesting with Wide Input Power Range.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

A 1~50mA 20ns Settling Time Low Dropout Regulator.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

A Low Power 16 Gbps CTLE and Quarter-Rate DFE With Single Adaptive System.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

A Prompt Engineering Approach to Scientific Text Simplification: CYUT at SimpleText2023 Task3.
Proceedings of the Working Notes of the Conference and Labs of the Evaluation Forum (CLEF 2023), 2023

SimpleText Best of Labs in CLEF-2022: Simplify Text Generation with Prompt Engineering.
Proceedings of the Experimental IR Meets Multilinguality, Multimodality, and Interaction, 2023

2022
CYUT Team2 SimpleText Shared Task Report in CLEF-2022.
Proceedings of the Working Notes of CLEF 2022 - Conference and Labs of the Evaluation Forum, Bologna, Italy, September 5th - to, 2022

2017
A 2.5 mW/ch, 50 Mcps, 10-Analog Channel, Adaptively Biased Read-Out Front-End IC With Low Intrinsic Timing Resolution for Single-Photon Time-of-Flight PET Applications With Time-Dependent Noise Analysis in 90 nm CMOS.
IEEE Trans. Biomed. Circuits Syst., 2017

A novel clock-pulse-width calibration technique for charge redistribution DACs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
A Distortion Cancelation Technique With the Recursive DFT Method for Successive Approximation Analog-to-Digital Converters.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC.
IEICE Electron. Express, 2016

A chaotically injected timing technique for ring-based oscillators.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

Low-voltage indoor energy harvesting using photovoltaic cell.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

Gm-C filter with automatic calibration scheme.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

2015
A 1.3 mW low-IF, current-reuse, and current-bleeding RF front-end for the MICS band with sensitivity of -97 dbm.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A 2.5 mW/ch, 50 Mcps, 10-analog channel, adaptively biased read-out front-end IC with 9.71 ps-RMS timing resolution for single-photon time-of-flight PET applications in 90 nm CMOS.
Proceedings of the VLSI Design, Automation and Test, 2015

A Synchronous Mirror Delay with Duty-Cycle Tunable Technology.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

Triangular Modulation Using Switched-Capacitor Scheme for Spread-Spectrum Clocking.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

PVT Insensitive High-Resolution Time to Digital Converter for Intraocular Pressure Sensing.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2014
A radio-controlled receiver for clocks/watches and alarm applications.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Analysis and design of a 1.3-mW current-reuse RF front-end for the MICS band.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A low supply voltage synchronous mirror delay with quadrature phase output.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

A 64-MHz∼640-MHz 64-phase clock generator.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

2013
A Low-Power Bio-Potential Acquisition System with Flexible PDMS Dry Electrodes for Portable Ubiquitous Healthcare Applications.
Sensors, 2013

Adaptive successive approximation ADC for biomedical acquisition system.
Microelectron. J., 2013

A low jitter delay-locked-loop applied for DDR4.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

Indoor energy harvesting using photovoltaic cell for battery recharging.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

External capacitorless low dropout linear regulator using cascode structure.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2012
A 0.6-V 800-MHz All-Digital Phase-Locked Loop With a Digital Supply Regulator.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

An Efficient Micro Control Unit with a Reconfigurable Filter Design for Wireless Body Sensor Networks (WBSNs).
Sensors, 2012

An MICS band frequency synthesizer using active inductor and auto-calibration scheme.
Microelectron. J., 2012

CMOS Differential Circuits Using Charge-Redistribution and Reduced-Swing Schemes.
IEICE Trans. Electron., 2012

A low voltage sigma delta modulator for temperature sensor.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

A low power analog front-end (AFE) circuit dedicated for driving bio-electrochemical sensors and peripheral devices.
Proceedings of the 2012 IEEE Biomedical Circuits and Systems Conference, 2012

2011
Time Multiplexed VLSI Architecture for Real-Time Barrel Distortion Correction in Video-Endoscopic Images.
IEEE Trans. Circuits Syst. Video Technol., 2011

A Low-Cost High-Quality Adaptive Scalar for Real-Time Multimedia Applications.
IEEE Trans. Circuits Syst. Video Technol., 2011

A 6-GHz Built-in Jitter Measurement Circuit Using Multiphase Sampler.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

Real-Time Telemetry System for Amperometric and Potentiometric Electrochemical Sensors.
Sensors, 2011

An Asynchronous Multi-Sensor Micro Control Unit for Wireless Body Sensor Networks (WBSNs).
Sensors, 2011

Differential bidirectional transceiver for on-chip long wires.
Microelectron. J., 2011

All digital phase-locked loop using active inductor oscillator and novel locking algorithm.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
Variable-Latency Floating-Point Multipliers for Low-Power Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Wide Dynamic Range CMOS Potentiostat for Amperometric Chemical Sensor.
Sensors, 2010

A Power-Efficient Bio-Potential Acquisition Device with DS-MDE Sensors for Long-Term Healthcare Monitoring Applications.
Sensors, 2010

A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2009
Wireless Body Sensor Network With Adaptive Low-Power Design for Biometrics and Healthcare Applications.
IEEE Syst. J., 2009

0.5V 160-MHz 260uW all digital phase-locked loop.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

Analysis and optimization of ring oscillator using sub-feedback scheme.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

2008
Frequency multiplier using 50% duty cycle corrector.
IEICE Electron. Express, 2008

All digital time-to-digital converter using single delay-locked loop.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

A 6-Gbit/s SATA spread-spectrum clock generator using two-stage delta-sigma modulator.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Low-power 50% duty cycle corrector.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Dual band LNA/mixer using conjugate matching for implantable biotelemetry.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Piecewise linear curvature-compensated CMOS bandgap reference.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Simultaneous bidirectional transceiver with impedance matching.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

CMOS bulk input current switch logic circuit.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
A New Cycle-Time-to-Digital Converter With Two Level Conversion Scheme.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

All-Digital PLL Using Pulse-Based DCO.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006
On-chip bidirectional transceiver.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

High-gain and high-bandwidth rail-to-rail operational amplifier with slew rate boost circuit.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

1-99% input duty 50% output duty cycle corrector.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
A 64-MHz~1920-MHz programmable spread-spectrum clock generator.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Interconnect accelerating techniques for sub-100-nm gigascale systems.
IEEE Trans. Very Large Scale Integr. Syst., 2004

A low-jitter mutual-correlated pulsewidth control loop circuit.
IEEE J. Solid State Circuits, 2004

Design and application of CMOS bulk input scheme.
IEEE J. Solid State Circuits, 2004

A low-voltage CMOS rail-to-rail operational amplifier using double p-channel differential input pairs.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
A high-bandwidth wireless infrared receiver with feedforward offset extractor.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
Low-power 2P2N SRAM with column hidden refresh.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

CMOS bulk input technique.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Input isolated sense amplifiers.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A time-delay-integration CMOS readout circuit for IR scanning.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

High-speed receivers for on-chip interconnections in deep-submicron process.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

Multiple bulk input differential logic.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

Threshold triggers and accelerator for deep submicron interconnection.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001
High-speed CMOS logic circuits in capacitor coupling technique.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

1995
Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994
New CMOS Differential Logic Circuits for True-Single-Phase Pipelined Systems.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993
Redundant Algebra and Integrated Circuit Implementation of Ternary Logic and Their Applications.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993


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