Hong Wang

According to our database, Hong Wang authored at least 42 papers between 1991 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2019

Visual Inertial Odometry At the Edge: A Hardware-Software Co-design Approach for Ultra-low Latency and Power.

Dipan Kumar Mandal, Srivatsava Jandhyala, Om Ji Omer, Gurpreet S. Kalsi, Biji George, Gopi Neela, Santhosh Kumar Rethinagiri, Sreenivas Subramoney, Lance Hacking, Jim Radford, Eagle Jones, Belliappa Kuttanna, Hong Wang

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

MARS: Memory Aware Reordered Source.

Ishwar Bhati, Udit Dhawan, Jayesh Gaur, Sreenivas Subramoney, Hong Wang

CoRR, 2018

Tackling memory access latency through DRAM row management.

Sriseshan Srikanth, Lavanya Subramanian, Sreenivas Subramoney, Thomas M. Conte, Hong Wang

Proceedings of the International Symposium on Memory Systems, 2018

Criticality Aware Tiered Cache Hierarchy: A Fundamental Relook at Multi-Level Cache Hierarchies.

Anant Nori, Jayesh Gaur, Siddharth Rai, Sreenivas Subramoney, Hong Wang

Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Density Tradeoffs of Non-Volatile Memory as a Replacement for SRAM Based Last Level Cache.

Kunal Korgaonkar, Ishwar Bhati, Huichu Liu, Jayesh Gaur, Sasikanth Manipatruni, Sreenivas Subramoney, Tanay Karnik, Steven Swanson, Ian Young, Hong Wang

Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Closed yet open DRAM: achieving low latency and high performance in DRAM memory systems.

Lavanya Subramanian, Kaushik Vaidyanathan, Anant Nori, Sreenivas Subramoney, Tanay Karnik, Hong Wang

Proceedings of the 55th Annual Design Automation Conference, 2018

2011

Bothnia: a dual-personality extension to the Intel integrated graphics driver.

Gautham N. Chinya, Jamison D. Collins, Perry H. Wang, Hong Jiang, Guei-Yuan Lueh, Thomas Piazza, Hong Wang

ACM SIGOPS Oper. Syst. Rev., 2011

Harmonia: a transparent, efficient, and harmonious dynamic binary translator targeting the Intel® architecture.

Guilherme Ottoni, Thomas Hartin, Christopher T. Weaver, Jason Brandt, Belliappa Kuttanna, Hong Wang

Proceedings of the 8th Conference on Computing Frontiers, 2011

AstroLIT: enabling simulation-based microarchitecture comparison between Intel® and Transmeta designs.

Guilherme Ottoni, Gautham N. Chinya, Gerolf Hoflehner, Jamison D. Collins, Amit Kumar, Ethan Schuchman, David R. Ditzel, Ronak Singhal, Hong Wang

Proceedings of the 8th Conference on Computing Frontiers, 2011

2010

Intel nehalem processor core made FPGA synthesizable.

Graham Schelle, Jamison D. Collins, Ethan Schuchman, Perry H. Wang, Xiang Zou, Gautham N. Chinya, Ralf Plate, Thorsten Mattner, Franz Olbrich, Per Hammarlund, Ronak Singhal, Jim Brayton, Sebastian Steibl, Hong Wang

Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

BLoG: post-silicon bug localization in processors using bug localization graphs.

Sung-Boem Park, Anne Bracy, Hong Wang, Subhasish Mitra

Proceedings of the 47th Design Automation Conference, 2010

2009

Criticality-based optimizations for efficient load processing.

Samantika Subramaniam, Anne Bracy, Hong Wang, Gabriel H. Loh

Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

Intel® atom^TM processor core made FPGA-synthesizable.

Perry H. Wang, Jamison D. Collins, Christopher T. Weaver, Belliappa Kuttanna, Shahram Salamian, Gautham N. Chinya, Ethan Schuchman, Oliver Schilling, Thorsten Doil, Sebastian Steibl, Hong Wang

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

2008

Mitosis: A Speculative Multithreaded Processor Based on Precomputation Slices.

Carlos Madriles, Carlos García Quiñones, F. Jesús Sánchez, Pedro Marcuello, Antonio González, Dean M. Tullsen, Hong Wang, John Paul Shen

IEEE Trans. Parallel Distributed Syst., 2008

CPR: Composable performance regression for scalable multiprocessor models.

Benjamin C. Lee, Jamison D. Collins, Hong Wang, David M. Brooks

Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

Processor Performance Modeling using Symbolic Simulation.

Omid Azizi, Jamison D. Collins, Dinesh Patil, Hong Wang, Mark Horowitz

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2008

Merge: a programming model for heterogeneous multi-core systems.

Michael D. Linderman, Jamison D. Collins, Hong Wang, Teresa H. Meng

Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems, 2008

Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor.

Henry Wong, Anne Bracy, Ethan Schuchman, Tor M. Aamodt, Jamison D. Collins, Perry H. Wang, Gautham N. Chinya, Ankur Khandelwal Groen, Hong Jiang, Hong Wang

Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008

2007

EXOCHI: architecture and programming environment for a heterogeneous multi-core multithreaded system.

Perry H. Wang, Jamison D. Collins, Gautham N. Chinya, Hong Jiang, Xinmin Tian, Milind Girkar, Nick Y. Yang, Guei-Yuan Lueh, Hong Wang

Proceedings of the ACM SIGPLAN 2007 Conference on Programming Language Design and Implementation, 2007

Sequencer virtualization.

Perry H. Wang, Jamison D. Collins, Gautham N. Chinya, Bernard Lint, Asit Mallick, Koichi Yamada, Hong Wang

Proceedings of the 21th Annual International Conference on Supercomputing, 2007

2006

Multiple Instruction Stream Processor.

Richard A. Hankins, Gautham N. Chinya, Jamison D. Collins, Perry H. Wang, Ryan N. Rakvic, Hong Wang, John Paul Shen

Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006

2005

A Dependency Chain Clustered Microarchitecture.

Satish Narayanasamy, Hong Wang, Perry H. Wang, John Paul Shen, Brad Calder

Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

2004

Helper Threads via Virtual Multithreading.

Perry H. Wang, Jamison D. Collins, Hong Wang, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore, John Paul Shen

IEEE Micro, 2004

Control Flow Optimization Via Dynamic Reconvergence Prediction.

Jamison D. Collins, Dean M. Tullsen, Hong Wang

Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004

Best of Both Latency and Throughput.

Ed Grochowski, Ronny Ronen, John Paul Shen, Hong Wang

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Hardware Support for Prescient Instruction Prefetch.

Tor M. Aamodt, Paul Chow, Per Hammarlund, Hong Wang, John Paul Shen

Proceedings of the 10th International Conference on High-Performance Computer Architecture (HPCA-10 2004), 2004

Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors.

Dongkeun Kim, Shih-Wei Liao, Perry H. Wang, Juan del Cuvillo, Xinmin Tian, Xiang Zou, Hong Wang, Donald Yeung, Milind Girkar, John Paul Shen

Proceedings of the 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 2004

Helper threads via virtual multithreading on an experimental itanium^® 2 processor-based platform.

Perry H. Wang, Jamison D. Collins, Hong Wang, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore, John Paul Shen

Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems, 2004

2003

A framework for modeling and optimization of prescient instruction prefetch.

Tor M. Aamodt, Pedro Marcuello, Paul Chow, Antonio González, Per Hammarlund, Hong Wang, John Paul Shen

Proceedings of the International Conference on Measurements and Modeling of Computer Systems, 2003

Inferno: a functional simulation infrastructure for modeling microarchitectural data speculations.

Hong Wang, Shiri Manor, Dave LaFollette, Nadav Nesher, Ku-jei King, Perry H. Wang, Shay Levy, Shai Satt, Gal Carmeli, Arjun Kapur, Ioannis Schoinas, Ed Rubinstein, Rahul Bhatt

Proceedings of the 2003 IEEE International Symposium on Performance Analysis of Systems and Software, 2003

2002

Post-Pass Binary Adaptation for Software-Based Speculative Precomputation.

Shih-Wei Liao, Perry H. Wang, Hong Wang, John Paul Shen, Gerolf Hoflehner, Daniel M. Lavery

Proceedings of the 2002 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 2002

Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation.

Perry H. Wang, Hong Wang, Jamison D. Collins, Ed Grochowski, Ralph-Michael Kling, John Paul Shen

Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002

Quantitative Evaluation of the Register Stack Engine and Optimizations for Future Itanium Processors.

R. David Weldon, Steven S. Chang, Hong Wang, Gerolf Hoflehner, Perry H. Wang, Daniel M. Lavery, John Paul Shen

Proceedings of the 6th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-6 2002), 2002

2001

Dynamic speculative precomputation.

Jamison D. Collins, Dean M. Tullsen, Hong Wang, John Paul Shen

Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

Speculative precomputation: long-range prefetching of delinquent loads.

Jamison D. Collins, Hong Wang, Dean M. Tullsen, Christopher J. Hughes, Yong-Fong Lee, Daniel M. Lavery, John Paul Shen

Proceedings of the 28th Annual International Symposium on Computer Architecture, 2001

Register Renaming and Scheduling for Dynamic Execution of Predicated Code.

Perry H. Wang, Hong Wang, Ralph-Michael Kling, Kalpana Ramakrishnan, John Paul Shen

Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 2001

2000

Redundant Arithmetic Optimizations (Research Note).

Thomas Y. Yeh, Hong Wang

Proceedings of the Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29, 2000

1997

Minimizing Area Cost of On-Chip Cache Memories by Caching Address Tags.

Hong Wang, Tong Sun, Qing Yang

IEEE Trans. Computers, 1997

1995

CAT - Caching Address Tags: A Technique for Reducing Area Cost of On-Chip Caches.

Hong Wang, Tong Sun, Qing Yang

Proceedings of the 22nd Annual International Symposium on Computer Architecture, 1995

1993

A New Graph Approach to Minimizing Processor Fragmentation in Hypercube Multiprocessors.

Qing Yang, Hong Wang

IEEE Trans. Parallel Distributed Syst., 1993

1992

On Fault-Tolerant Computation of Orthogonal Transforms on Hypercube Computers.

Qing Yang, Hong Wang

Proceedings of the 1992 International Conference on Parallel Processing, 1992

1991

Prime Cube Graph Approach for Processor Allocation in Hypercube Multiprocessors.

Hong Wang, Qing Yang

Proceedings of the International Conference on Parallel Processing, 1991