Hong-Thu Nguyen

Orcid: 0000-0002-9522-2903

According to our database1, Hong-Thu Nguyen authored at least 22 papers between 2015 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
A 0.9-V 50-MHz 256-bit 1D-to-2D-based single/multi-match priority encoder with 0.67-nW standby power on 65-nm SOTB CMOS.
Microprocess. Microsystems, 2020

2019
An Efficient I/O Architecture for RAM-Based Content-Addressable Memory on FPGA.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 1.2-V 162.9 pJ/cycle bitmap index creation core with 0.31-pW/bit standby power on 65-nm SOTB.
Microprocess. Microsystems, 2019

2018
A Low-Power Hybrid Adaptive CORDIC.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A High-Throughput Low-Energy Arithmetic Processor.
IEICE Trans. Electron., 2018

A CORDIC-based QR decomposition for MIMO signal detector.
IEICE Electron. Express, 2018

An FPGA-Based Hardware Accelerator for Energy-Efficient Bitmap Index Creation.
IEEE Access, 2018

VLSI Design of Frequent Items Counting Using Binary Decoders Applied to 8-bit per Item Case-study.
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018

A 219-μW 1D-to-2D-Based Priority Encoder on 65-nm SOTB CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

An efficient fixed-point arithmetic processor using a hybrid CORDIC algorithm.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
A Scalable High-Performance Priority Encoder Using 1D-Array to 2D-Array Conversion.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

A Low-Latency Parallel Pipeline CORDIC.
IEICE Trans. Electron., 2017

FPGA-based frequent items counting using matrix of equality comparators.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Highly parallel bitmap-based regular expression matching for text analytics.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
An FPGA approach for high-performance multi-match priority encoder.
IEICE Electron. Express, 2016

An FPGA approach for fast bitmap indexing.
IEICE Electron. Express, 2016

An efficient FPGA-based database processor for fast database analytics.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A hybrid adaptive CORDIC in 65nm SOTB CMOS process.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A high-throughput and low-power design for bitmap indexing on 65-nm SOTB CMOS process.
Proceedings of the International Conference on IC Design and Technology, 2016

2015
Low-resource low-latency hybrid adaptive CORDIC with floating-point precision.
IEICE Electron. Express, 2015

Parallel pipelining configurable multi-port memory controller for multimedia applications.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

SAR: A Self-Adaptive and Reliable protocol for wireless multimedia sensor networks.
Proceedings of the Seventh International Conference on Ubiquitous and Future Networks, 2015


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