Hong-Sun Hwang

According to our database¹, Hong-Sun Hwang authored at least 6 papers between 1989 and 2015.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of three.

Timeline

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In proceedings

Article

PhD thesis

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Bibliography

2015

The classification methodology of chip quality using canonical correlation analysis-based variable selection on chip level data.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Conference on Industrial Engineering and Engineering Management, 2015

2011

An Area-Efficient, Low-VDD, Highly Reliable Multi-Cell Antifuse System Fully Operative in DRAMs.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2011

2010

A highly reliable multi-cell antifuse scheme using DRAM cell capacitors.

[BibT_eX]

[DOI]

Proceedings of the 36th European Solid-State Circuits Conference, 2010

2005

A 4-Gb/s/pin low-power memory I/O interface using 4-level simultaneous bi-directional signaling.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2005

1999

A 2.5-V, 72-Mbit, 2.0-GByte/s packet-based DRAM with a 1.0-Gbps/pin interface.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 1999

1989

An experimental 16-Mbit DRAM with reduced peak-current noise.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, October, 1989

Hong-Sun Hwang

Timeline

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On csauthors.net:

Bibliography

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