Hong-Ru Chou
According to our database1,
Hong-Ru Chou
authored at least 9 papers
between 2016 and 2019.
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Bibliography
2019
Flexible design and implementation of QC-Based LDPC decoder architecture for on-line user-defined matrix downloading and efficient decoding.
Integr., 2019
2018
Design and Implementation of Flexible and Reconfigurable SDF-Based FFT Chip Architecture With Changeable-Radix Processing Elements.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
VLSI Design and Implementation of Reconfigurable 46-Mode Combined-Radix-Based FFT Hardware Architecture for 3GPP-LTE Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
VLSI design and implementation of a reconfigurable hardware-friendly Polar encoder architecture for emerging high-speed 5G system.
Integr., 2018
Reconfigurable VLSI design of a changeable hybrid-radix FFT hardware architecture with 2D-FIFO storing structure for 3GPP LTE systems.
ICT Express, 2018
2017
48-Mode Reconfigurable Design of SDF FFT Hardware Architecture Using Radix-3<sup>2</sup> and Radix-2<sup>3</sup> Design Approaches.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
Reconfigurable hardware design of low-area-cost computing kernel engine for different radixes of single-path delay feedback FFT systems.
Proceedings of the IEEE International Conference on Consumer Electronics, 2017
A 2-D grouping FIFO based hardware architecture for supporting 36-mode hybrid-radix FFT design in 3GPP-LTE systems.
Proceedings of the IEEE 6th Global Conference on Consumer Electronics, 2017
2016
Reconfigurable VLSI design of processing kernel for multiple-radix single-path delay feedback FFT systems.
Proceedings of the IEEE 5th Global Conference on Consumer Electronics, 2016