Hong-Chen Cheng
According to our database1,
Hong-Chen Cheng
authored at least 5 papers
between 2012 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
A 3-nm FinFET 27.6-Mbit/mm<sup>2</sup> Single-Port 6T SRAM Enabling 0.48-1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking.
IEEE J. Solid State Circuits, April, 2024
A 3nm Fin-FET 19.87-Mbit/mm<sup>2</sup> 2RW Pseudo Dual-Port 6T SRAM with High-R Wire Tracking and Sequential Access Aware Dynamic Power Reduction.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2012
A 28nm high-k metal-gate SRAM with Asynchronous Cross-Couple Read Assist (AC<sup>2</sup>RA) circuitry achieving 3x reduction on speed variation for single ended arrays.
Proceedings of the Symposium on VLSI Circuits, 2012