Hon Nin Cheung

According to our database1, Hon Nin Cheung authored at least 9 papers between 1995 and 2001.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of six.

Timeline

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Bibliography

2001
Hardware implementation of the depth first search bit stream SPIHT system.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
A dataflow-oriented VLSI architecture for a modified SPIHT algorithm using depth-first search bit stream processing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Parallel Architecture for the Implementation of the Embedded Zerotree Wavelet Algorithm.
Proceedings of the 5th Australasian Computer Architecture Conference (ACAC 2000), 31 January, 2000

1999
Smart pixel VLSI architecture for embedded zerotree wavelet coding.
Proceedings of the ISSPA '99. Proceedings of the Fifth International Symposium on Signal Processing and its Applications, 1999

Robust image compression using the depth-first search on the wavelet zerotree.
Proceedings of the ISSPA '99. Proceedings of the Fifth International Symposium on Signal Processing and its Applications, 1999

EZW algorithm using depth-first representation of the wavelet zerotree.
Proceedings of the ISSPA '99. Proceedings of the Fifth International Symposium on Signal Processing and its Applications, 1999

VLSI decoder architecture for embedded zerotree wavelet algorithm.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

An Efficient Aopproach to Constrained Via Minimization for Two-Layer VLSI Routing.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1995
Counterpropagation network and time-frequency shift-tolerant preprocessing for phoneme recognition.
Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995


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