Holger Eisenreich

According to our database¹, Holger Eisenreich authored at least 24 papers between 2009 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of three.

Timeline

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In proceedings

Article

PhD thesis

Dataset

Other

Links

On csauthors.net:

Bibliography

2024

EdgeVision SoC: PPA-Impact of RTL-level Modifications.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE International System-on-Chip Conference, 2024

2023

A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI.

[BibT_eX]

[DOI]

Proceedings of the 20th International SoC Design Conference, 2023

2021

IC Design & Technology Co-Development: e-NVM & mmWave enablement of 22FDX™ Technology.

[BibT_eX]

[DOI]

Proceedings of the International Conference on IC Design and Technology, 2021

2020

Adaptive Body Bias Aware Implementation for Ultra-Low-Voltage Designs in 22FDX Technology.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2020

A 0.55V 6.3uW/MHz Arm Cortex-M4 MCU with Adaptive Reverse Body Bias and Single Rail SRAM.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE Symposium in Low-Power and High-Speed Chips, 2020

2019

A Fast Lock-In Ultra Low-Voltage ADPLL Clock Generator with Adaptive Body Biasing in 22nm FDSOI Technology.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

How to Achieve World-Leading Energy Efficiency using 22FDX with Adaptive Body Biasing on an Arm Cortex-M4 IoT SoC.

[BibT_eX]

[DOI]

Proceedings of the 49th European Solid-State Device Research Conference, 2019

2017

Exploration of FPGA architectures for tight coupled accelerators in a 22nm FDSOI technology.

[BibT_eX]

[DOI]

Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017

A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

An MPSoC for energy-efficient database query processing.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

2015

An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2015

A deep-submicron CMOS flow for general-purpose timing-detection insertion.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference Mixed Design of Integrated Circuits & Systems, 2015

2014

10.7 A 105GOPS 36mm2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A compact on-chip IR-drop measurement system in 28 nm CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

A Fast-Locking ADPLL With Instantaneous Restart Capability in 28-nm CMOS Technology.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2013

Live demonstration: A 90GBit/s serial NoC link over 6mm in 65nm CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

2012

A 32 GBit/s communication SoC for a waferscale neuromorphic system.

[BibT_eX]

[DOI]

Integr., 2012

A 335Mb/s 3.9mm2 65nm CMOS flexible MIMO detection-decoding engine achieving 4G wireless data rates.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A power management architecture for fast per-core DVFS in heterogeneous MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2010

Efficient compensation of delay variations in high-speed network-on-chip data links.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010

Low power design of the X-GOLD® SDR 20 baseband processor.

[BibT_eX]

[DOI]

Wolfgang Raab

Jörg Berthold

J. A. Ulrich Hachmann

Proceedings of the Design, Automation and Test in Europe, 2010

2009

A novel ADPLL design using successive approximation frequency control.

[BibT_eX]

[DOI]

Microelectron. J., 2009

Holger Eisenreich

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