Holger Blume

Orcid: 0000-0002-0640-6875

Affiliations:
  • University of Hanover, Germany


According to our database1, Holger Blume authored at least 166 papers between 1996 and 2024.

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Bibliography

2024
PTP-Synchronized Tri-Level Sync Generation for Networked Multi-Sensor Systems.
Proceedings of the 30th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2024


Learning of Multimodal Point Descriptors in Radar and LIDAR Point Clouds.
Proceedings of the IEEE International Conference on Multisensor Fusion and Integration for Intelligent Systems, 2024

Sub-Microsecond Time Synchronization for Network-Connected Microcontrollers.
Proceedings of the IEEE International Conference on Consumer Electronics, 2024

Design Space Exploration of Semantic Segmentation CNN SalsaNext for Constrained Architectures.
Proceedings of the 35th IEEE International Conference on Application-specific Systems, 2024

Multi-Level Prototyping of a Vertical Vector AI Processing System.
Proceedings of the 35th IEEE International Conference on Application-specific Systems, 2024

Enhancing a Hearing Aid Processor with ISA Extensions Supporting Flexible Fixed-Point Formats.
Proceedings of the 35th IEEE International Conference on Application-specific Systems, 2024

2023
Design and Evaluation of a 180 nm Powerline Communication ASIC for Harsh Environment.
Microprocess. Microsystems, March, 2023

Dynamic Model-Based Safety Margins for High-Density Matrix Headlight Systems.
IEEE Trans. Intell. Transp. Syst., 2023

Fault Detection Mechanisms for COTS FPGA Systems Used in Low Earth Orbit.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023

High Performance Instruction Fetch Structure within a RISC-V Processor for Use in Harsh Environments.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023

Online Quantization Adaptation for Fault-Tolerant Neural Network Inference.
Proceedings of the Computer Safety, Reliability, and Security, 2023

N<sup>2</sup>V<sup>2</sup>PRO: Neural Network Mapping Framework for a Custom Vector Processor Architecture.
Proceedings of the 13th IEEE International Conference on Consumer Electronics - Berlin, 2023

Improved Multi-Scale Grid Rendering of Point Clouds for Radar Object Detection Networks.
Proceedings of the 26th International Conference on Information Fusion, 2023

Fault Detection on Multi COTS FPGA Systems for Physics Experiments on the International Space Station.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

A High-Performance, Low Power Research Hearing Aid featuring a High-Level Programmable Custom 22nm FDSOI SoC.
Proceedings of the 45th Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2023


The ZuSE-KI-Mobil AI Accelerator SoC: Overview and a Functional Safety Perspective.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Exploiting Subword Permutations to Maximize CNN Compute Performance and Efficiency.
Proceedings of the 34th IEEE International Conference on Application-specific Systems, 2023

2022
A Survey on Application Specific Processor Architectures for Digital Hearing Aids.
J. Signal Process. Syst., 2022

Predictive accuracy of CNN for cortical oscillatory activity in an acute rat model of parkinsonism.
Neural Networks, 2022

Methodology for an Early Exploration of Embedded Systems using Portable Test and Stimulus Standard.
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022

Implementing Synthetic Aperture Radar Backprojection in Chisel - A Field Report.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022

A Silicon-Proof Controller System for Flexible Ultra-Low-Power Energy Harvesting Platforms.
Proceedings of the 11th International Conference on Modern Circuits and Systems Technologies, 2022

Self-Supervised Velocity Estimation for Automotive Radar Object Detection Networks.
Proceedings of the 2022 IEEE Intelligent Vehicles Symposium, 2022

Improved Orientation Estimation and Detection with Hybrid Object Detection Networks for Automotive Radar.
Proceedings of the 25th IEEE International Conference on Intelligent Transportation Systems, 2022

Fault-tolerant Radar Signal Processing using Selective Observation Windows and Peak Detection.
Proceedings of the 30th European Signal Processing Conference, 2022

SmartHeaP - A High-level Programmable, Low Power, and Mixed-Signal Hearing Aid SoC in 22nm FD-SOI.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

Automatically Controlled Flow and Pressure Conditions in a Bioreactor System for Medium- to Large-Sized Tissue-Engineered Vascular Grafts.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2022

2021
Correction to: Multicore Performance Prediction with MPET.
J. Signal Process. Syst., 2021

Evaluation of Different Processor Architecture Organizations for On-Site Electronics in Harsh Environments.
Int. J. Parallel Program., 2021

Powerline Communication System-on-Chip in 180 nm Harsh Environment SOI Technology.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2021, Oslo, 2021

Measuring vertical jump height using a smartphone camera with simultaneous gravity-based calibration.
Proceedings of the IEEE International Conference on Consumer Electronics, 2021

Psychophysical Study of Human Visual Perception of Flicker Artifacts in Automotive Digital Mirror Replacement Systems.
Proceedings of the Human Vision and Electronic Imaging 2021, Virtual Event, January 2021., 2021

Markerless Camera-Based Vertical Jump Height Measurement Using OpenPose.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition Workshops, 2021

2020
Multicore Performance Prediction with MPET.
J. Signal Process. Syst., 2020

Design Space Exploration Framework for Tensilica-Based Digital Audio Processors in Hearing Aids.
Proceedings of the 9th International Conference on Modern Circuits and Systems Technologies, 2020

Issue-Slot Based Predication Encoding Technique for VLIW Processors.
Proceedings of the 9th International Conference on Modern Circuits and Systems Technologies, 2020

Psychophysics Study on LED Flicker Artefacts for Automotive Digital Mirror Replacement Systems.
Proceedings of the Human Vision and Electronic Imaging 2020, 2020

CereBridge: An Efficient, FPGA-based Real-Time Processing Platform for True Mobile Brain-Computer Interfaces.
Proceedings of the 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2020

Automated Bioreactor System for the Cultivation of Autologous Tissue-Engineered Vascular Grafts.
Proceedings of the 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2020

2019
Online stereo camera calibration for automotive vision based on HW-accelerated A-KAZE-feature extraction.
J. Syst. Archit., 2019

Dynamic self-reconfiguration of a MIPS-based soft-core processor architecture.
J. Parallel Distributed Comput., 2019

FLINT+: A runtime-configurable emulation-based stochastic timing analysis framework.
Integr., 2019

KAVUAKA: A Low Power Application Specific Hearing Aid Processor.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Design and Optimization of an ARM Cortex-M Based SoC for TCP/IP Communication in High Temperature Applications.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

Evaluation of Different Processor Architecture Organizations for On-site Electronics in Harsh Environments.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

A Rapport and Gait Monitoring System Using a Single Head-Worn IMU during Walk and Talk.
Proceedings of the IEEE International Conference on Consumer Electronics, 2019

Deep Learning Based Classification of Pedestrian Vulnerability Trained on Synthetic Datasets.
Proceedings of the 9th IEEE International Conference on Consumer Electronics, 2019

Probabilistic 3D Point Cloud Fusion on Graphics Processors for Automotive (Poster).
Proceedings of the 22th International Conference on Information Fusion, 2019

Multicore Performance Prediction - Comparing Three Recent Approaches in a Case Study.
Proceedings of the Euro-Par 2019: Parallel Processing Workshops, 2019

Statistical Performance Prediction for Multicore Applications Based on Scalability Characteristics.
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018
Real-Time Gait Analysis Using a Single Head-Worn Inertial Measurement Unit.
IEEE Trans. Consumer Electron., 2018

A Hardware Efficient Preamble Detection Algorithm for Powerline Communication.
J. Commun., 2018

Low-Cost Channel Sounder Design Based on Software-Defined Radio and OFDM.
Proceedings of the 88th IEEE Vehicular Technology Conference, 2018

GPU-enhanced Multimodal Dense Matching.
Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018

Transport-Triggered Soft Cores.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

Real-Time LED Flicker Detection and Mitigation: Architecture and FPGA-Implementation.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Selective LED Flicker Detection and Mitigation Algorithm for Non-HDR Video Sequences.
Proceedings of the 8th IEEE International Conference on Consumer Electronics - Berlin, 2018

A HOG-based Real-time and Multi-scale Pedestrian Detector Demonstration System on FPGA.
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

2017
Small footprint synthesizable temperature sensor for FPGA devices.
J. Syst. Archit., 2017

FPGA emulation methodology for fast and accurate power estimation of embedded processors.
J. Syst. Archit., 2017

Balanced application-specific processor system for efficient SIFT-feature detection.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Using a genetic algorithm approach to reduce register file pressure during instruction scheduling.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Analyzing the trade-off between power consumption and beamforming algorithm performance using a hearing aid ASIP.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

SF<sup>3</sup>: A scalable and flexible FPGA-framework for education and rapid prototyping.
Proceedings of the 2017 IEEE International Conference on Microelectronic Systems Education, 2017

Portable Implementation of Advanced Driver-Assistance Algorithms on Heterogeneous Architectures.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

Real-time implementation of a GMM-based binaural localization algorithm on a VLIW-SIMD processor.
Proceedings of the 2017 IEEE International Conference on Multimedia and Expo, 2017

Tool-supported design space exploration of a processor system for SIFT-feature detection.
Proceedings of the 7th IEEE International Conference on Consumer Electronics - Berlin, 2017

High Performance and Low Power Architectures: GPU vs. FPGA for Fast Factorized Backprojection.
Proceedings of the Fifth International Symposium on Computing and Networking, 2017

FPGA Accelerated NoC-Simulation: A Case Study on the Intel Xeon Phi Ringbus Topology.
Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017

Performance estimation of indoor optical wireless communication systems using OMNeT++.
Proceedings of the 22nd IEEE International Workshop on Computer Aided Modeling and Design of Communication Links and Networks, 2017

A mobile electrochemical (bio-)sensor node for a vascular graft bioreactor.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

2016
Analyzing the Performance-Hardware Trade-off of an ASIP-based SIFT Feature Extraction.
J. Signal Process. Syst., 2016

Design space exploration of hardware platforms for interactive low latency movement sonification.
J. Multimodal User Interfaces, 2016

Efficient Emulation of Floating-Point Arithmetic on Fixed-Point SIMD Processors.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

An FPGA architecture for velocity independent backprojection in FMCW-based SAR systems.
Proceedings of the 2016 IEEE International Symposium on Signal Processing and Information Technology, 2016

Dynamic Self-Reconfiguration of a MIPS-Based Soft-Processor Architecture.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

Customized high performance low power processor for binaural speaker localization.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Real-time gait event detection using a single head-worn inertial measurement unit.
Proceedings of the IEEE 6th International Conference on Consumer Electronics - Berlin, 2016

Hardware acceleration of Maximum-Likelihood angle estimation for automotive MIMO radars.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

A toolchain for the 3D-visualization of bioartificial vascular grafts based on ultrasound images.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

FPGA-based frequency estimation of a DFB laser using Rb spectroscopy for space missions.
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

2015
An area efficient real- and complex-valued multiply-accumulate SIMD unit for digital signal processors.
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015

Energy- and latency-aware simulation of battery-operated wireless embedded networks for home automation.
Proceedings of the 10th IEEE International Symposium on Industrial Embedded Systems, 2015

FNOCEE: A framework for NoC evaluation by FPGA-based emulation.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Abstracting Parallel Programming and Its Analysis Towards Framework Independent Development.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

Hardware accelerator for minimum mean square error interference alignment.
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015

A real-time monitoring system controller for medical tissue engineering bioreactors.
Proceedings of the IEEE International Conference on Consumer Electronics, 2015

A mobile SoC-based platform for evaluating hearing aid algorithms and architectures.
Proceedings of the IEEE 5th International Conference on Consumer Electronics - Berlin, 2015

Implementation and analysis of the histograms of oriented Gradients algorithm on a heterogeneous multicore CPU/GPU architecture.
Proceedings of the 2015 IEEE Global Conference on Signal and Information Processing, 2015

FLINT: layout-oriented FPGA-based methodology for fault tolerant ASIC design.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Fast and accurate power estimation for application-specific instruction set processors using FPGA emulation.
Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing, 2015

An electronic encapsulated monitoring system for a vascular graft bioreactor.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

A Synthesizable Temperature Sensor on FPGA Using DSP-Slices for Reduced Calibration Overhead and Improved Stability.
Proceedings of the Architecture of Computing Systems - ARCS 2015, 2015

Exploring Dynamic Reconfigurable CORDIC Co-Processors Tightly Coupled with a VLIW-SIMD Soft-Processor Architecture.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014
Reliable orientation estimation for mobile motion capturing in medical rehabilitation sessions based on inertial measurement units.
Microelectron. J., 2014

Customizing a VLIW-SIMD application-specific instruction-set processor for hearing aid devices.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Instruction-set extension for an ASIP-based SIFT feature extraction.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

Massively parallel signal processing challenges within a driver assistant prototype framework first case study results with a novel MIMO-radar.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

A comprehensive ASIC/FPGA prototyping environment for exploring embedded processing systems for advanced driver assistance applications.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

Performance evaluation of the Intel Xeon Phi manycore architecture using parallel video-based driver assistance algorithms.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

Hardware-assisted power estimation for design-stage processors using FPGA emulation.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

Design space exploration of hardware architectures for content based music classification.
Proceedings of the IEEE International Conference on Consumer Electronics, 2014

Real-time low latency movement sonification in stroke rehabilitation based on a mobile platform.
Proceedings of the IEEE International Conference on Consumer Electronics, 2014

HLS-based FPGA implementation of a predictive block-based motion estimation algorithm - A field report.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014

ASEV - Automatic situation assessment for event-driven video analysis.
Proceedings of the 11th IEEE International Conference on Advanced Video and Signal Based Surveillance, 2014

2013
High Performance Hardware Architectures for Automated Music Classification.
Proceedings of the Algorithms from and for Nature and Life, 2013

Architectures for Stereo Vision.
Proceedings of the Handbook of Signal Processing Systems, 2013

Using SDRAM Memories for High-Performance Accesses to Two-Dimensional Matrices Without Transpose.
Int. J. Parallel Program., 2013

Parallel implementation of real-time semi-global matching on embedded multi-core architectures.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

Project-organized education: From FPGA prototyping to ASIC design: Consecutive microelectronic education in designing application-specific hardware.
Proceedings of the 2013 IEEE International Conference on Microelectronic Systems Education, 2013

Mobile and wireless inertial sensor platform for motion capturing in stroke rehabilitation sessions.
Proceedings of the 5th IEEE International Workshop on Advances in Sensors and Interfaces, 2013

Energy-efficient inertial sensor fusion on heterogeneous FPGA-fabric/RISC System on Chip.
Proceedings of the Seventh International Conference on Sensing Technology, 2013

Hardware-accelerator design for energy-efficient acoustic feature extraction.
Proceedings of the IEEE 2nd Global Conference on Consumer Electronics, 2013

Enhanced motion estimation for driver assistance systems - Integration of a curved road model.
Proceedings of the IEEE 2nd Global Conference on Consumer Electronics, 2013

Modification and fixed-point analysis of a Kalman filter for orientation estimation based on 9D inertial measurement unit data.
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013

2012
Special session on "FPGA-based emulation of hardware architectures".
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Model-based improvement of motion vector fields for driver assistance systems.
Proceedings of the IEEE Second International Conference on Consumer Electronics - Berlin, 2012

Evaluation of Inertial Sensor Fusion Algorithms in Grasping Tasks Using Real Input Data: Comparison of Computational Costs and Root Mean Square Error.
Proceedings of the 2012 Ninth International Conference on Wearable and Implantable Body Sensor Networks, 2012

2011
Huge Music Archives on Mobile Devices.
IEEE Signal Process. Mag., 2011

A hardware accelerated configurable ASIP architecture for embedded real-time video-based driver assistance applications.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Using SDRAMs for two-dimensional accesses of long 2<sup>n</sup> × 2<sup>m</sup>-point FFTs and transposing.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Real-time semi-global matching disparity estimation on the GPU.
Proceedings of the IEEE International Conference on Computer Vision Workshops, 2011

A FPGA architecture for real-time processing of variable-length FFTS.
Proceedings of the IEEE International Conference on Acoustics, 2011

Instruction set extension for high throughput disparity estimation in stereo image processing.
Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011

2010
A fully programmable FSM-based Processing Engine for Gigabytes/s header parsing.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

Real-time stereo vision system using semi-global matching disparity estimation: Architecture and FPGA-implementation.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

Mapping of a Real-Time Object Detection Application onto a Configurable RISC/Coprocessor Architecture at Full HD Resolution.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

A forwarding-sensitive instruction scheduling approach to reduce register file constraints in VLIW architectures.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

2009
Introduction to the Special Issue on SAMOS 2007.
J. Signal Process. Syst., 2009

Hardware-based synchronization framework for heterogeneous RISC/Coprocessor architectures.
Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009

Instruction merging to increase parallelism in VLIW architectures.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009

2008
Application Domain Specific Embedded FPGAs for Flexible ISA-Extension of ASIPs.
J. Signal Process. Syst., 2008

A Scalable Packet Sorting Circuit for High-Speed WFQ Packet Scheduling.
IEEE Trans. Very Large Scale Integr. Syst., 2008

OpenMP-based parallelization on an MPCore multiprocessor platform - A performance and power analysis.
J. Syst. Archit., 2008

ASIP-eFPGA Architecture for Multioperable GNSS Receivers.
Proceedings of the Embedded Computer Systems: Architectures, 2008

Perceptual feature based music classification - A DSP perspective for a new type of application.
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

Design of a Pareto-optimization environment and its application to motion estimation.
Proceedings of the International Workshop on Multimedia Signal Processing, 2008

Design flow for embedded FPGAs based on a flexible architecture template.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Application of deterministic and stochastic Petri-Nets for performance modeling of NoC architectures.
J. Syst. Archit., 2007

Hybrid functional- and instruction-level power modeling for embedded and heterogeneous processor architectures.
J. Syst. Archit., 2007

Performance and Power Analysis of Parallelized Implementations on an MPCore Multiprocessor Platform.
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007

Programmable Architectures for Realtime Music Decompression.
Proceedings of the Parallel Computing: Architectures, 2007

A Power Estimation Model for an FPGA-based Softcore Processor.
Proceedings of the FPL 2007, 2007

2006
A Case Study for the Application of Deterministic and Stochastic Petri Nets in the SoC Communication Domain.
J. VLSI Signal Process., 2006

Hybrid Functional and Instruction Level Power Modeling for Embedded Processors.
Proceedings of the Embedded Computer Systems: Architectures, 2006

Modelling and Quantitative Analysis of Coupling Mechanisms of Programmable Processor Cores and Arithmetic Oriented eFPGA Macros.
Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, 2006

Konstruktion und Etablierung einer Klimakammer für die Untersuchung der embryonalen Herzentwicklung.
Proceedings of the Bildverarbeitung für die Medizin 2006, Algorithmen, Systeme, Anwendungen, Proceedings des Workshops vom 19., 2006

Quantitative Analysis of Embedded FPGA-Architectures for Arithmetic.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

Design and Analysis of Matching Circuit Architectures for a Closest Match Lookup.
Proceedings of the Advanced International Conference on Telecommunications and International Conference on Internet and Web Applications and Services (AICT/ICIW 2006), 2006

2005
Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip.
J. VLSI Signal Process., 2005

Modeling NoC Architectures by Means of Deterministic and Stochastic Petri Nets.
Proceedings of the Embedded Computer Systems: Architectures, 2005

2004
Segmentation in the loop: an iterative object-based algorithm for motion estimation.
Proceedings of the Visual Communications and Image Processing 2004, 2004

Performance Analysis of SoC Communication by Application of Deterministic and Stochastic Petri Nets.
Proceedings of the Computer Systems: Architectures, 2004

2002
Embedding of Dedicated High-Performance ASICs into Reconfigurable Systems Providing Additional Multimedia Functionality.
J. VLSI Signal Process., 2002

Object based refinement of motion vector fields applying probabilistic homogenization rules.
IEEE Trans. Consumer Electron., 2002

Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip.
Proceedings of the 13th IEEE International Conference on Application-Specific Systems, 2002

2000
A Hardware Implementation for Approximate Text Search in Multimedia Applications.
Proceedings of the 2000 IEEE International Conference on Multimedia and Expo, 2000

Integration of High-Performance ASICs into Reconfigurable Systems Providing Additional Multimedia Functionality.
Proceedings of the 12th IEEE International Conference on Application-Specific Systems, 2000

1999
Nonlinear vector error tolerant interpolation of intermediate video images by weighted medians.
Signal Process. Image Commun., 1999

1998
FIR-filter design with spatial and frequency design constraints using evolution strategies.
Signal Process., 1998

1997
Nichtlineare fehlertolerante Interpolation von Zwischenbildern.
PhD thesis, 1997

New algorithm for nonlinear vector-based upconversion with center weighted medians.
J. Electronic Imaging, 1997

Optimizing Video Signal Processing Algorithms by Evolution Strategies.
Proceedings of the Computational Intelligence, 1997

1996
Vector-based nonlinear upconversion applying center-weighted medians.
Proceedings of the Nonlinear Image Processing VII, 1996


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