Hojin Park

According to our database, Hojin Park authored at least 38 papers between 2003 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Understanding open-set recognition by Jacobian norm and inter-class separation.

Jaewoo Park, Hojin Park, Eunju Jeong, Andrew Beng Jin Teoh

Pattern Recognit., January, 2024

Reducing Cross-Cloud/Region Costs with the Auto-Configuring MACARON Cache.

Hojin Park, Ziyue Qiu, Gregory R. Ganger, George Amvrosiadis

Proceedings of the ACM SIGOPS 30th Symposium on Operating Systems Principles, 2024

Face Reconstruction Transfer Attack as Out-of-Distribution Generalization.

Yoon Gyo Jung, Jaewoo Park, Xingbo Dong, Hojin Park, Andrew Beng Jin Teoh, Octavia I. Camps

Proceedings of the Computer Vision - ECCV 2024, 2024

2023

Mimir: Finding Cost-efficient Storage Configurations in the Public Cloud.

Hojin Park, Gregory R. Ganger, George Amvrosiadis

Proceedings of the 16th ACM International Conference on Systems and Storage, 2023

Minimum Assumption Reconstruction Attacks: Rise of Security and Privacy Threats Against Face Recognition.

Dezhi Li, Hojin Park, Xingbo Dong, Yen-Lung Lai, Hui Zhang, Andrew Beng Jin Teoh, Zhe Jin

Proceedings of the Pattern Recognition and Computer Vision - 6th Chinese Conference, 2023

Pretrained Implicit-Ensemble Transformer for Open-Set Authentication on Multimodal Mobile Biometrics.

Jaeho Yoon, Jaewoo Park, Kensuke Wagata, Hojin Park, Andrew Beng Jin Teoh

Proceedings of the 31st ACM International Conference on Multimedia, 2023

Towards Query Efficient and Generalizable Black-Box Face Reconstruction Attack.

Hojin Park, Jaewoo Park, Xingbo Dong, Andrew Beng Jin Teoh

Proceedings of the IEEE International Conference on Image Processing, 2023

2022

Understanding Open-Set Recognition by Jacobian Norm of Representation.

Jaewoo Park, Hojin Park, Eunju Jeong, Andrew Beng Jin Teoh

CoRR, 2022

Open-Set Face Identification on Few-Shot Gallery by Fine-Tuning.

Hojin Park, Jaewoo Park, Andrew Beng Jin Teoh

Proceedings of the 26th International Conference on Pattern Recognition, 2022

2020

An Asynchronous Boost Converter With Time-Based Dual-Mode Control for Wide Load Range and High Efficiency in SSD Applications.

Kyoungjin Lee, Haneul Kim, Jehyung Yoon, Hyoung-Seok Oh, Jin-Hong Park, Byeong-Ha Park, Hojin Park, Yoonmyung Lee

IEEE Trans. Ind. Electron., 2020

More IOPS for Less: Exploiting Burstable Storage in Public Clouds.

Hojin Park, Gregory R. Ganger, George Amvrosiadis

Proceedings of the 12th USENIX Workshop on Hot Topics in Cloud Computing, 2020

2019

Automating System Configuration of Distributed Machine Learning.

Woo-Yeon Lee, Markus Weimer, Brian Cho, Byung-Gon Chun, Yunseong Lee, Joo Seong Jeong, Gyeong-In Yu, Jooyeon Kim, Hojin Park, Beomyeol Jeon, Won Wook Song, Gunhee Kim

Proceedings of the 39th IEEE International Conference on Distributed Computing Systems, 2019

Parallax: Sparsity-aware Data Parallel Training of Deep Neural Networks.

Soojeong Kim, Gyeong-In Yu, Hojin Park, Sungwoo Cho, Eunji Jeong, Hyeonmin Ha, Sanha Lee, Joo Seong Jeong, Byung-Gon Chun

Proceedings of the Fourteenth EuroSys Conference 2019, Dresden, Germany, March 25-28, 2019, 2019

2018

Parallax: Automatic Data-Parallel Training of Deep Neural Networks.

Soojeong Kim, Gyeong-In Yu, Hojin Park, Sungwoo Cho, Eunji Jeong, Hyeonmin Ha, Sanha Lee, Joo Seong Jeong, Byung-Gon Chun

CoRR, 2018

2017

A 0.015-mm² Inductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology.

Gyu-Seob Jeong, Wooseok Kim, Jaejin Park, Taeik Kim, Hojin Park, Deog-Kyoon Jeong

IEEE Trans. Circuits Syst. II Express Briefs, 2017

2016

19.3 A 2.4GHz 1.5mW digital MDLL using pulse-width comparator and double injection technique in 28nm CMOS.

Hyunik Kim, Yongjo Kim, Taeik Kim, Hojin Park, SeongHwan Cho

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

A 0.35-0.5-V 18-152 MHz Digitally Controlled Relaxation Oscillator With Adaptive Threshold Calibration in 65-nm CMOS.

Yudong Zhang, Woogeun Rhee, Taeik Kim, Hojin Park, Zhihua Wang

IEEE Trans. Circuits Syst. II Express Briefs, 2015

14.8 A 0.009mm² 2.06mW 32-to-2000MHz 2^nd-order ΔΣ analogous bang-bang digital PLL with feed-forward delay-locked and phase-locked operations in 14nm FinFET technology.

Minyoung Song, Taeik Kim, Jihyun F. Kim, Wooseok Kim, Sung-Jin Kim, Hojin Park

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

14.4 A 5GHz -95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS.

Hyojun Kim, Jinwoo Sang, Hyunik Kim, Youngwoo Jo, Taeik Kim, Hojin Park, SeongHwan Cho

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

15.5 A 0.6V 1.17ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with 16× spatial redundancy in 14nm FinFET technology.

Sung-Jin Kim, Wooseok Kim, Minyoung Song, Jihyun F. Kim, Taeik Kim, Hojin Park

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

A 72μW, 2.4GHz, 11.7% tuning range, 212dBc/Hz FoM LC-VCO in 65nm CMOS.

Joo-Myoung Kim, Jae-Seung Lee, Sun-a Kim, Taeik Kim, Hojin Park, Sang-Gug Lee

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014

Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator.

Wooseok Kim, Jaejin Park, Hojin Park, Deog-Kyoon Jeong

IEEE J. Solid State Circuits, 2014

A 0.63ps, 12b, synchronous cyclic TDC using a time adder for on-chip jitter measurement of a SoC in 28nm CMOS technology.

Sung-Jin Kim, Taeik Kim, Hojin Park

Proceedings of the Symposium on VLSI Circuits, 2014

15.2 A 0.012mm² 3.1mW bang-bang digital fractional-N PLL with a power-supply-noise cancellation technique and a walking-one-phase-selection fractional frequency divider.

Jenlung Liu, Tae-Kwang Jang, Yonghee Lee, Jungeun Shin, Seunghoon Lee, Taeik Kim, Jaejin Park, Hojin Park

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A 0.010mm² 9.92psrms low tracking jitter pixel clock generator with a divider initializer and a nearest phase selector in 28nm CMOS technology.

Kangyeop Choo, Sung-Jin Kim, Wooseok Kim, Jihyun F. Kim, Taeik Kim, Hojin Park

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013

10-315-MHz Cascaded Hybrid Phase-Locked Loop for Pixel Clock Generation.

Minyoung Song, Young-Ho Kwak, Sunghoon Ahn, Hojin Park, Chulwoo Kim

IEEE Trans. Very Large Scale Integr. Syst., 2013

A 0.032mm² 3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range.

Wooseok Kim, Jaejin Park, Jihyun F. Kim, Taeik Kim, Hojin Park, Deog-Kyoon Jeong

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A 0.026mm² 5.3mW 32-to-2000MHz digital fractional-N phase locked-loop using a phase-interpolating phase-to-digital converter.

Tae-Kwang Jang, Nan Xing, Frank Liu, Jungeun Shin, Hyungreal Ryu, Jihyun F. Kim, Taeik Kim, Jaejin Park, Hojin Park

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Verifying start-up failures in coupled ring oscillators in presence of variability using predictive global optimization.

Taehwan Kim, Do-Gyoon Song, Sangho Youn, Jaejin Park, Hojin Park, Jaeha Kim

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

2012

An all-digital clock generator using a fractionally injection-locked oscillator in 65nm CMOS.

Pyoungwon Park, Jaejin Park, Hojin Park, SeongHwan Cho

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 0.004mm² 250μW ΔΣ TDC with time-difference accumulator and a 0.012mm² 2.5mW bang-bang digital PLL using PRNG for low-power SoC applications.

Jong-Phil Hong, Sung-Jin Kim, Jenlung Liu, Nan Xing, Tae-Kwang Jang, Jaejin Park, Jihyun F. Kim, Taeik Kim, Hojin Park

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011

EAFR-based DLNA proxy for high-quality video distribution in extended home space.

Taein Hwang, Hojin Park, Euihyun Paik, Jinwook Chung

IEEE Trans. Consumer Electron., 2011

A 0.8V, sub-mW, varactor-tuning ring-oscillator-based clock generator in 32nm CMOS.

Jenlung Liu, Sehyung Jeon, Tae-Kwang Jang, Dohyung Kim, Jihyun F. Kim, Jaejin Park, Hojin Park

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2009

Interoperability model for devices over heterogeneous home networks.

Hojin Park, Moonok Choi, Euihyun Paik, Nam Kim

IEEE Trans. Consumer Electron., 2009

2008

Architecture of home gateway for device collaboration in extended home space.

Hojin Park, Ilwoo Lee, Taein Hwang, Nam Kim

IEEE Trans. Consumer Electron., 2008

Personal Mobile A/V Control Point for Home-to-Home Media Streaming.

Taein Hwang, Hojin Park, Jinwook Chung

IEEE Trans. Consumer Electron., 2008

2007

Design of a Digital Home Service Delivery and Management System for OSGi Framework.

Taein Hwang, Hojin Park, Jin-Wook Chung

Proceedings of the Managing Next Generation Networks and Services, 2007

2003

3.3-V baseband Gm-C filters for wireless transceiver applications.

Jaeyoung Shin, Sunki Min, Soosun Kim, Joongho Choi, Soohyoung Lee, Hojin Park, Jaewhui Kim

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003