Hoeseok Yang
Orcid: 0000-0002-7929-7470
According to our database1,
Hoeseok Yang
authored at least 58 papers
between 2007 and 2024.
Collaborative distances:
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Bibliography
2024
CoRR, 2024
To Balance or to Not? Battery Aging-Aware Active Cell Balancing for Electric Vehicles.
CoRR, 2024
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
Proceedings of the IEEE International Conference on Robotics and Automation, 2024
Platform Design for Privacy-Preserving Federated Learning using Homomorphic Encryption : Wild-and-Crazy-Idea Paper.
Proceedings of the Forum on Specification & Design Languages, 2024
2023
A Runtime Switchable Multi-Phase Convolutional Neural Network for Resource-Constrained Systems.
IEEE Access, 2023
2021
Real-Time Schedulability Analysis and Enhancement of Transiently Powered Processors With NVMs.
IEEE Trans. Computers, 2021
Des. Autom. Embed. Syst., 2021
IEEE Access, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Optimal Partitioning of Distributed Neural Networks for Various Communication Environments.
Proceedings of the International Conference on Artificial Intelligence in Information and Communication, 2021
Proceedings of the Euro-Par 2021: Parallel Processing, 2021
2020
Reliability Optimization of Real-Time Satellite Embedded System Under Temperature Variations.
IEEE Access, 2020
Improvement of CNN-Based Road Extraction from Satellite Images via Morphological Image Processing.
Proceedings of the IEEE International Geoscience and Remote Sensing Symposium, 2020
2019
Optimization of Fault-Tolerant Mixed-Criticality Multi-Core Systems with Enhanced WCRT Analysis.
ACM Trans. Design Autom. Electr. Syst., 2019
Measurement-Based Power Optimization Technique for OpenCV on Heterogeneous Multicore Processor.
Symmetry, 2019
Temperature Sensor Assisted Lifetime Enhancement of Satellite Embedded Systems via Multi-Core Task Mapping and DVFS.
Sensors, 2019
Efficiently Switchable Context-Aware Dataflow Adaptation Technique for Low-Power Multi-Core Embedded Systems.
IEEE Access, 2019
Proceedings of the 2019 International Conference on Information and Communication Technology Convergence, 2019
Proceedings of the 2019 International Conference on Information and Communication Technology Convergence, 2019
A SIMD-aware pruning technique for convolutional neural networks with multi-sparsity levels: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion, 2019
2018
Context-aware dataflow adaptation technique for low-power multi-core embedded systems.
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
Proceedings of the International Symposium on Rapid System Prototyping, 2017
2016
A Formal Approach to Power Optimization in CPSs With Delay-Workload Dependence Awareness.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Power Optimization of Multimode Mobile Embedded Systems with Workload-Delay Dependency.
Mob. Inf. Syst., 2016
IEICE Electron. Express, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the 7th International Conference on Ambient Systems, 2016
2015
Modeling and power optimization of cyber-physical systems with energy-workload tradeoff.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
2014
EURETILE D7.3 - Dynamic DAL benchmark coding, measurements on MPI version of DPSNN-STDP (distributed plastic spiking neural net) and improvements to other DAL codes.
CoRR, 2014
COOLIP: Simple yet effective job allocation for distributed thermally-throttled processors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 2014 International Conference on Compilers, 2014
2013
Predictability for timing and temperature in multiprocessor system-on-chip platforms.
ACM Trans. Embed. Comput. Syst., 2013
Real Time Syst., 2013
Efficient Worst-Case Temperature Evaluation for Thermal-Aware Assignment of Real-Time Applications on MPSoCs.
J. Electron. Test., 2013
Reliable and Efficient Execution of Multiple Streaming Applications on Intel's SCC Processor.
Proceedings of the Euro-Par 2013: Parallel Processing Workshops, 2013
Expandable process networks to efficiently specify and explore task, data, and pipeline parallelism.
Proceedings of the International Conference on Compilers, 2013
2012
IET Circuits Devices Syst., 2012
Proceedings of the 2012 IEEE 18th Real Time and Embedded Technology and Applications Symposium, 2012
Fast worst-case peak temperature evaluation for real-time applications on multi-core systems.
Proceedings of the 13th Latin American Test Workshop, 2012
Multi-objective mapping optimization via problem decomposition for many-core systems.
Proceedings of the IEEE 10th Symposium on Embedded Systems for Real-time Multimedia, 2012
Scenario-based design flow for mapping streaming applications onto on-chip many-core systems.
Proceedings of the 15th International Conference on Compilers, 2012
Power agnostic technique for efficient temperature estimation of multicore embedded systems.
Proceedings of the 15th International Conference on Compilers, 2012
2011
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011
Proceedings of the Formal Methods for Components and Objects, 10th International Symposium, 2011
Proceedings of the Formal Methods for Components and Objects, 10th International Symposium, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the 48th Design Automation Conference, 2011
2010
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
2009
Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis.
J. Signal Process. Syst., 2008
2007
Performance evaluation and optimization of dual-port SDRAM architecture for mobile embedded systems.
Proceedings of the 2007 International Conference on Compilers, 2007