Hoang Minh Le

Orcid: 0000-0002-8957-4144

Affiliations:
  • University of Bremen, Institute of Computer Science, Germany


According to our database1, Hoang Minh Le authored at least 57 papers between 2005 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2024
OPSurv: Orthogonal Polynomials Quadrature Algorithm for Survival Analysis.
CoRR, 2024

2023
GamutMLP: A Lightweight MLP for Color Loss Recovery.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023

2022
3D DDoA-based Self-Positioning of Mobile Devices.
Proceedings of the 30th European Signal Processing Conference, 2022

2021
3D Self-Positioning Algorithm based on joint DDoA-ToA.
Proceedings of the 3rd IEEE Middle East and North Africa COMMunications Conference, 2021

2D DoA-based Positioning with Phase Jump Corrections and An Approximate Maximum Likelihood Estimator.
Proceedings of the 3rd IEEE Middle East and North Africa COMMunications Conference, 2021

GamutNet: Restoring Wide-Gamut Colors for Camera-Captured Images.
Proceedings of the 29th Color and Imaging Conference, 2021

2D DDoA-based Self-Positioning for Mobile Devices.
Proceedings of the 29th European Signal Processing Conference, 2021

Online Robust Control of Nonlinear Systems with Large Uncertainty.
Proceedings of the 24th International Conference on Artificial Intelligence and Statistics, 2021

2020
Improving Color Space Conversion for Camera-Captured Images via Wide-Gamut Metadata.
Proceedings of the 28th Color and Imaging Conference, 2020

LLVM-based Hybrid Fuzzing with LibKluzzer (Competition Contribution).
Proceedings of the Fundamental Approaches to Software Engineering, 2020

A Geometric Interpretation of Trilateration for RSS-based Localization.
Proceedings of the 28th European Signal Processing Conference, 2020

2019
Verifying SystemC Using Intermediate Verification Language and Stateful Symbolic Simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Combining sequentialization-based verification of multi-threaded C programs with symbolic Partial Order Reduction.
Int. J. Softw. Tools Technol. Transf., 2019

Diagnosis and monitoring of Alzheimer's patients using classical and deep learning techniques.
Expert Syst. Appl., 2019

Property-Driven Timestamps Encoding for Timeprints-Based Tracing and Monitoring.
Proceedings of the Formal Modeling and Analysis of Timed Systems, 2019

Detection of Hardware Trojans in SystemC HLS Designs via Coverage-guided Fuzzing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Verifying Instruction Set Simulators using Coverage-guided Fuzzing<sup>*</sup>.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Data Flow Testing for SystemC-AMS Timed Data Flow Models.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Temporal Tracing of On-Chip Signals using Timeprints.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Early Concolic Testing of Embedded Binaries with Virtual Prototypes: A RISC-V Case Study.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

KLUZZER: Whitebox Fuzzing on Top of LLVM.
Proceedings of the Automated Technology for Verification and Analysis, 2019

Maximizing power state cross coverage in firmware-based power management.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Towards Automated Refinement of TLM Properties to RTL.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2018

Extensible and Configurable RISC-V Based Virtual Prototype.
Proceedings of the 2018 Forum on Specification & Design Languages, 2018

Resilience evaluation via symbolic fault injection on intermediate code.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Towards fully automated TLM-to-RTL property refinement.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Testbench qualification for SystemC-AMS timed data flow models.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Early SoC security validation by VP-based static information flow analysis.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Towards Early Validation of Firmware-Based Power Management Using Virtual Prototypes: A Constrained Random Approach.
Proceedings of the Languages, Design Methods, and Tools for Electronic System Design, 2017

Data flow testing for virtual prototypes.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Guided lightweight Software test qualification for IP integration using Virtual Prototypes.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Compiled symbolic simulation for systemC.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

On the application of formal fault localization to automated RTL-to-TLM fault correspondence analysis for fast and accurate VP-based error effect simulation - a case study.
Proceedings of the 2016 Forum on Specification and Design Languages, 2016

Towards formal verification of real-world SystemC TLM peripheral models - a case study.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

ParCoSS: Efficient Parallelized Compiled Symbolic Simulation.
Proceedings of the Computer Aided Verification - 28th International Conference, 2016

2015
Automated techniques for functional verification at the electronic system level.
PhD thesis, 2015

Funktionale Verifikation eingebetteter Systeme: Techniken und Werkzeuge auf Systemebene.
Proceedings of the Ausgezeichnete Informatikdissertationen 2015, 2015

Verifying SystemC using stateful symbolic simulation.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Lazy-CSeq-SP: Boosting Sequentialization-Based Verification of Multi-threaded C Programs via Symbolic Pruning of Redundant Schedules.
Proceedings of the Automated Technology for Verification and Analysis, 2015

2014
Self-Verification as the Key Technology for Next Generation Electronic Systems.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

Funktionale Abdeckungsanalyse von C-Programmen.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2014

Towards verifying determinism of SystemC designs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014


2013
Scalable fault localization for SystemC TLM designs.
Proceedings of the Design, Automation and Test in Europe, 2013

Verifying SystemC using an intermediate verification language and symbolic simulation.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Automatic TLM Fault Localization for SystemC.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

CRAVE: An Advanced Constrained RAndom Verification Environment for SystemC.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2012

From Requirements and Scenarios to ESL Design in SystemC.
Proceedings of the International Symposium on Electronic System Design, 2012

Completeness-Driven Development.
Proceedings of the Graph Transformations - 6th International Conference, 2012

The system verification methodology for advanced TLM verification.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2010
Automatic Fault Localization for SystemC TLM Designs.
Proceedings of the 11th International Workshop on Microprocessor Test and Verification, 2010

Proving transaction and system-level properties of untimed SystemC TLM designs.
Proceedings of the 8th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010), 2010

Towards analyzing functional coverage in SystemC TLM property checking.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

2009
Induction-Based Formal Verification of SystemC TLM Designs.
Proceedings of the 10th International Workshop on Microprocessor Test and Verification, 2009

Formal Verification of Abstract SystemC Models.
Proceedings of the Algorithms and Applications for Next Generation SAT Solvers, 08.11., 2009

2008
Quantified Synthesis of Reversible Logic.
Proceedings of the Design, Automation and Test in Europe, 2008

2005
Computations of the symmetric cosine transform using Forsythe and Clenshaw's recurrence formulae.
Proceedings of the Electronic Imaging: Image and Video Communications and Processing 2005, 2005


  Loading...