Hitoshi Yamanaka

According to our database, Hitoshi Yamanaka authored at least 3 papers between 2003 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2007

Design Methodology for 2.4GHz Dual-Core Microprocessor.

Noriyuki Ito, Hiroaki Komatsu, Akira Kanuma, Akihiro Yoshitake, Yoshiyasu Tanamura, Hiroyuki Sugiyama, Ryoichi Yamashita, Ken-ichi Nabeya, Hironobu Yoshino, Hitoshi Yamanaka, Masahiro Yanagida, Yoshitomo Ozeki, Kinya Ishizaka, Takeshi Kono, Yutaka Isoda

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Delay defect screening for a 2.16GHz SPARC64 microprocessor.

Noriyuki Ito, Akira Kanuma, Daisuke Maruyama, Hitoshi Yamanaka, Tsuyoshi Mochizuki, Osamu Sugawara, Chihiro Endoh, Masahiro Yanagida, Takeshi Kono, Yutaka Isoda, Kazunobu Adachi, Takahisa Hiraide, Shigeru Nagasawa, Yaroku Sugiyama, Eizo Ninoi

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2003

BIST-Aided Scan Test - A New Method for Test Cost Reduction.

Takahisa Hiraide, Kwame Osei Boateng, Hideaki Konishi, Koichi Itaya, Michiaki Emori, Hitoshi Yamanaka, Takashi Mochiyama

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003