Hitoshi Shiga

According to our database1, Hitoshi Shiga authored at least 11 papers between 1999 and 2012.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2012
A 151-mm<sup>2</sup> 64-Gb 2 Bit/Cell NAND Flash Memory in 24-nm CMOS Technology.
IEEE J. Solid State Circuits, 2012

2011

2009
A 16 Gb 3-Bit Per Cell (X3) NAND Flash Memory on 56 nm Technology With 8 MB/s Write Rate.
IEEE J. Solid State Circuits, 2009


2008

2007
A 56-nm CMOS 99-mm<sup>2</sup> 8-Gb Multi-Level NAND Flash Memory With 10-MB/s Program Throughput.
IEEE J. Solid State Circuits, 2007

2006

2002
A 44-mm<sup>2</sup> four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller.
IEEE J. Solid State Circuits, 2002

2001
Wordline voltage generating system for low-power low-voltage flash memories.
IEEE J. Solid State Circuits, 2001

2000
A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme.
IEEE J. Solid State Circuits, 2000

1999
A CMOS bandgap reference circuit with sub-1-V operation.
IEEE J. Solid State Circuits, 1999


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