Hisayasu Sato
According to our database1,
Hisayasu Sato
authored at least 15 papers
between 1989 and 2022.
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Bibliography
2022
A 22nm 0.84mm<sup>2</sup> BLE Transceiver With Self IQ-Phase Correction Achieving 39dB Image Rejection and on-Chip Antenna Impedance Tuning.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2015
13.4 A 6.3mW BLE transceiver embedded RX image-rejection filter and TX harmonic-suppression filter reusing on-chip matching network.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2013
A Multiband LTE SAW-Less CMOS Transmitter with Source-Follower-Driven Passive Mixers, Envelope-Tracked RF-PGAs, and Marchand Baluns.
IEICE Trans. Electron., 2013
2012
A digital PLL with two-step closed-locking for multi-mode/multi-band SAW-less transmitter.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
A Wide Dynamic Range Variable Gain Amplifier with Enhanced IP1 dB and Temperature Compensation.
IEICE Trans. Electron., 2011
2007
A 1.8 mm<sup>2</sup>, 11 mA, 23.2 dB-NF, discrete-time filter for GSM/WCDMA/WLAN using retiming technique.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2003
IEEE J. Solid State Circuits, 2003
Proceedings of the ESSCIRC 2003, 2003
2002
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
2001
A 2.4-GHz-band 1.8-V operation single-chip Si-CMOS T/R-MMIC front-end with a low insertion loss switch.
IEEE J. Solid State Circuits, 2001
1998
IEEE J. Solid State Circuits, 1998
1996
A fully compensated active pull-down ECL circuit with self-adjusting driving capability.
IEEE J. Solid State Circuits, 1996
IEEE J. Solid State Circuits, 1996
1994
IEEE J. Solid State Circuits, October, 1994
1989
IEEE J. Solid State Circuits, October, 1989