Hisashi Iwamoto

According to our database, Hisashi Iwamoto authored at least 14 papers between 2012 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

28-m W Fully Embedded AI Techniques with On-site Learning for Low-Power Handy Tactile Sensing System.

Yuji Yano, Hisashi Iwamoto, Takuma Yoshimura, Yoshihiro Nishida, Tatsuya Mori, Kiyotaka Komoku, Hidekuni Takao, Kazutami Arimoto

Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022

2017

A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA (Abstract Only).

Hiroki Nakahara, Haruyoshi Yonekawa, Hisashi Iwamoto, Masato Motomura

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

2016

An Update Method for a Low Power Cam Emulator Using an LUT Cascade Based on an EVMDD (<i>k</i>).

Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Hisashi Iwamoto

J. Multiple Valued Log. Soft Comput., 2016

LUT Cascades Based on Edge-Valued Multi-Valued Decision Diagrams: Application to Packet Classification.

Hiroki Nakahara, Tsutomu Sasao, Hisashi Iwamoto, Munehiro Matsuura

IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

A memory-based realization of a binarized deep convolutional neural network.

Hiroki Nakahara, Haruyoshi Yonekawa, Tsutomu Sasao, Hisashi Iwamoto, Masato Motomura

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Energy-efficient high-speed search engine using a multi-dimensional TCAM architecture with parallel pipelined subdivided structure.

Masami Nawa, Kenzo Okuda, Shingo Ata, Yasuto Kuroda, Yuji Yano, Hisashi Iwamoto, Kazunari Inoue, Ikuo Oka

Proceedings of the 13th IEEE Annual Consumer Communications & Networking Conference, 2016

2015

A Memory-Based IPv6 Lookup Architecture Using Parallel Index Generation Units.

Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Hisashi Iwamoto, Yasuhiro Terao

IEICE Trans. Inf. Syst., 2015

2013

A study on micro level traffic prediction for energy-aware routers.

Sou Koyano, Shingo Ata, Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Kazunari Inoue, Ikuo Oka

ACM SIGOPS Oper. Syst. Rev., 2013

A 250 Msps, 0.5 W eDRAM-Based Search Engine Dedicated Low Power FIB Application.

Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Koji Yamamoto, Kazunari Inoue, Ikuo Oka

IEICE Trans. Electron., 2013

Deterministic Packet Buffer System with Multi FIFO Queues for the Advanced QoS.

Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Koji Yamamoto, Shingo Ata, Kazunari Inoue

IEICE Trans. Commun., 2013

2D Sliced Packet Buffer with traffic volume and buffer occupancy adaptation for power saving.

Kenzo Okuda, Shingo Ata, Yasuto Kuroda, Yuji Yano, Hisashi Iwamoto, Kazunari Inoue, Ikuo Oka

Proceedings of the 10th IEEE Consumer Communications and Networking Conference, 2013

2012

A slice structure using the management of network traffic prediction for green IT.

Yuji Yano, Hisashi Iwamoto, Yasuto Kuroda, Shiro Ohtani, Shingo Ata, Kazunari Inoue

Proceedings of the 13th IEEE International Conference on High Performance Switching and Routing, 2012

A 200Msps, 0.6W eDRAM-based search engine applying full-route capacity dedicated FIB application.

Yasuto Kuroda, Yuji Yano, Hisashi Iwamoto, Koji Yamamoto, Kazunari Inoue, Masahiro Suzuki

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

Deterministic High Density Packet-Buffer System for Low Cost Network Systems.

Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Koji Yamamoto, Shingo Ata, Kazunari Inoue

Proceedings of the IEEE 26th International Conference on Advanced Information Networking and Applications, 2012