Hisanori Hamano

According to our database1, Hisanori Hamano authored at least 3 papers between 1992 and 1998.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

1992
1993
1994
1995
1996
1997
1998
0
1
2
1
1
1

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

1998
A low power SRAM using auto-backgate-controlled MT-CMOS.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

1997
A Floating Point Divider using Redundant Binary Circuits and an Asynchronous Clock Scheme.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1992
A 100-MHz 4-Mb cache DRAM with fast copy-back scheme.
IEEE J. Solid State Circuits, November, 1992


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