Hisakatsu Yamaguchi

According to our database, Hisakatsu Yamaguchi authored at least 25 papers between 2003 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

Training Deep Neural Networks in 8-bit Fixed Point with Dynamic Shared Exponent Management.

Hisakatsu Yamaguchi, Makiko Ito, Katsuhiro Yoda, Atsushi Ike

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2019

Event-Driven Model for High Speed End-to-End Simulations of Transmission System with Non-Linear Optical Elements and Cascaded Clock-and-Data Recovery Circuits.

Jun Matsui, Hisakatsu Yamaguchi

Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

2018

On-Chip Jitter Measurement Using Jitter Injection in a 28 Gb/s PI-Based CDR.

Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Hisakatsu Yamaguchi

IEEE J. Solid State Circuits, 2018

Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs.

Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Yuuki Ogata, Hisakatsu Yamaguchi

IEEE J. Solid State Circuits, 2018

2017

A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS.

Wahid Rahman, Danny Yoo, Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Takayuki Shibasaki, Hisakatsu Yamaguchi

IEEE J. Solid State Circuits, 2017

6.6 A 22.5-to-32Gb/s 3.2pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28nm CMOS.

Wahid Rahman, Danny Yoo, Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Takayuki Shibasaki, Hisakatsu Yamaguchi

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

6.7 A 28Gb/s digital CDR with adaptive loop gain for optimum jitter tolerance.

Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Yuuki Ogata, Hisakatsu Yamaguchi

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Jitter injection for on-chip jitter measurement in PI-based CDRs.

Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Hisakatsu Yamaguchi

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016

A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS.

Hiroki Miyaoka, Futoshi Terasawa, Masahiro Kudo, Hideki Kano, Atsushi Matsuda, Noriaki Shirai, Shigeaki Kawai, Takayuki Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura, Yutaka Ide, Kazuhiro Terashima, Hirohito Higashi, Tomokazu Higuchi, Naoaki Naka

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS.

Takayuki Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, Hiroki Miyaoka, Futoshi Terasawa, Masahiro Kudo, Hideki Kano, Atsushi Matsuda, Shigeaki Kawai, Tomoyuki Arai, Hirohito Higashi, Naoaki Naka, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2014

A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution.

Takushi Hashida, Yasumoto Tomita, Yuuki Ogata, Kosuke Suzuki, Shigeto Suzuki, Takanori Nakao, Yuji Terao, Satofumi Honda, Sota Sakabayashi, Ryuichi Nishiyama, Akihiko Konmoto, Yoshitomo Ozeki, Hiroyuki Adachi, Hisakatsu Yamaguchi, Yoichi Koyanagi, Hirotaka Tamura

Proceedings of the Symposium on VLSI Circuits, 2014

F6: Energy-efficient I/O design for next-generation systems.

Frank O'Mahony, Nicola Da Dalt, Ken Chang, Hisakatsu Yamaguchi, Chulwoo Kim, Elad Alon

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013

Session 2 overview: Ultra-high-speed transceivers and equalizers.

Ken Chang, Hisakatsu Yamaguchi

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

F3: Emerging technologies for wireline communication.

Elad Alon, Azita Emami, Gerrit den Besten, Ichiro Fujimori, Tadahiro Kuroda, Masafumi Nogawa, Hisakatsu Yamaguchi

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012

10-40 Gb/s I/O design for data communications.

Ken Chang, Tony Chan Carusone, Ali Sheikholeslami, Bob Payne, Miki Moyal, John T. Stonick, Hisakatsu Yamaguchi

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2010

A 5-Gb/s ADC-Based Feed-Forward CDR in 65 nm CMOS.

Oleksiy Tyshchenko, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune, Hisakatsu Yamaguchi, Junji Ogawa

IEEE J. Solid State Circuits, 2010

A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS.

Hisakatsu Yamaguchi, Hirotaka Tamura, Yoshiyasu Doi, Yasumoto Tomita, Takayuki Hamada, Masaya Kibune, Shuhei Ohmoto, Keita Tateishi, Oleksiy Tyshchenko, Ali Sheikholeslami, Tomokazu Higuchi, Junji Ogawa, Tamio Saito, Hideki Ishida, Kohtaroh Gotoh

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A fractional-sampling-rate ADC-based CDR with feedforward architecture in 65nm CMOS.

Oleksiy Tyshchenko, Ali Sheikholeslami, Hirotaka Tamura, Yasumoto Tomita, Hisakatsu Yamaguchi, Masaya Kibune, Takuji Yamamoto

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2008

Event-Driven Modeling of CDR Jitter Induced by Power-Supply Noise, Finite Decision-Circuit Bandwidth, and Channel ISI.

Marcus van Ierssel, Hisakatsu Yamaguchi, Ali Sheikholeslami, Hirotaka Tamura, William W. Walker

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

20-GHz Quadrature Injection-Locked LC Dividers With Enhanced Locking Range.

Takayuki Shibasaki, Hirotaka Tamura, Kouichi Kanda, Hisakatsu Yamaguchi, Junji Ogawa, Tadahiro Kuroda

IEEE J. Solid State Circuits, 2008

2007

18-GHz Clock Distribution Using a Coupled VCO Array.

Takayuki Shibasaki, Hirotaka Tamura, Kouichi Kanda, Hisakatsu Yamaguchi, Junji Ogawa, Tadahiro Kuroda

IEICE Trans. Electron., 2007

2006

Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies.

Hirotaka Tamura, Masaya Kibune, Hisakatsu Yamaguchi, Kouichi Kanda, Kohtaroh Gotoh, Hideki Ishida, Junji Ogawa

IEICE Trans. Electron., 2006

2005

A 5-6.4-Gb/s 12-channel transceiver with pre-emphasis and equalization.

Hirohito Higashi, Syunitirou Masaki, Masaya Kibune, Satoshi Matsubara, Takaya Chiba, Yoshiyasu Doi, Hisakatsu Yamaguchi, Hideki Takauchi, Hideki Ishida, Kohtaroh Gotoh, Hirotaka Tamura

IEEE J. Solid State Circuits, 2005

A 0.8-1.3V 16-channel 2.5Gb/s high-speed serial transceiver in a 90nm standard CMOS process.

Yoshiyasu Doi, Syunitirou Masaki, Takaya Chiba, Hirohito Higashi, Hisakatsu Yamaguchi, Hideki Takauchi, Hideki Ishida, Kohtaroh Gotoh, Junji Ogawa, Hirotaka Tamura

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2003

A CMOS multichannel 10-Gb/s transceiver.

Hideki Takauchi, Hirotaka Tamura, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takaya Chiba, Hideaki Anbutsu, Hisakatsu Yamaguchi, Toshihiko Mori, Motomu Takatsu, Kohtaroh Gotoh, Toshiaki Sakai, Takeshi Yamamura

IEEE J. Solid State Circuits, 2003