Hiroyuki Yotsuyanagi

According to our database, Hiroyuki Yotsuyanagi authored at least 67 papers between 1995 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Test Point Selection for Multi-Cycle Logic BIST using Multivariate Temporal-Spatial GCNs.

Senling Wang, Shaoqi Wei, Hisashi Okamoto, Tatusya Nishikawa, Hiroshi Kai, Yoshinobu Higami, Hiroyuki Yotsuyanagi, Ruijun Ma, Tianming Ni, Hiroshi Takahashi, Xiaoqing Wen

Proceedings of the IEEE International Test Conference in Asia, 2024

2023

On Test Pattern Generation Method for an Approximate Multiplier Considering Acceptable Faults.

Shogo Tokai, Daichi Akamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume

Proceedings of the IEEE International Test Conference in Asia, 2023

2022

Enhanced Interconnect Test Method for Resistive Open Defects in Final Tests with Relaxation Oscillators.

Masao Ohmatsu, Yuto Ohtera, Yuki Ikiri, Hiroyuki Yotsuyanagi, Shyue-Kung Lu, Masaki Hashizume

Proceedings of the IEEE 31st Asian Test Symposium, 2022

2020

Fault-Aware Dependability Enhancement Techniques for Flash Memories.

Shyue-Kung Lu, Shu-Chi Yu, Chun-Lung Hsu, Chi-Tien Sun, Masaki Hashizume, Hiroyuki Yotsuyanagi

IEEE Trans. Very Large Scale Integr. Syst., 2020

2019

On Delay Measurement Under Delay Variations in Boundary Scan Circuit with Embedded TDC.

Shuya Kikuchi, Hiroyuki Yotsuyanagi, Masaki Hashizume

Proceedings of the IEEE International Test Conference in Asia, 2019

Electrical Field Test Method of Resistive Open Defects between Dies by Quiescent Currents through Embedded Diodes.

Hanna Soneda, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu

Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

On Delay Elements in Boundary Scan Cells for Delay Testing of 3D IC Interconnection.

Toshiaki Satoh, Hiroyuki Yotsuyanagi, Masaki Hashizume

Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

2018

A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs.

Fara Ashikin, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu, Zvi Roth

IEICE Trans. Inf. Syst., 2018

A Sequentially Untestable Fault Identification Method Based on n-Bit State Cube Justification.

Toshinori Hosokawa, Morito Niseki, Masayoshi Yoshimura, Hiroshi Yamazaki, Masayuki Arai, Hiroyuki Yotsuyanagi, Masaki Hashizume

Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Test Time Reduction on Testing Delay Faults in 3D ICs Using Boundary Scan Design.

Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume

Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017

Discrimination of a Resistive Open Using Anomaly Detection of Delay Variation Induced by Transitions on Adjacent Lines.

Hiroyuki Yotsuyanagi, Kotaro Ise, Masaki Hashizume, Yoshinobu Higami, Hiroshi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

A defect level monitor of resistive open defect at interconnects in 3D ICs by injected charge volume.

Kouhei Ohtani, Naho Osato, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu

Proceedings of the 17th International Symposium on Communications and Information Technologies, 2017

On selection of adjacent lines in test pattern generation for delay faults considering crosstalk effects.

Yuuya Ohama, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami, Hiroshi Takahashi

Proceedings of the 17th International Symposium on Communications and Information Technologies, 2017

A defective level monitor of open defects in 3D ICs with a comparator of offset cancellation type.

Michiya Kanda, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

Fault-Aware Page Address Remapping Techniques for Enhancing Yield and Reliability of Flash Memories.

Shyue-Kung Lu, Shu-Chi Yu, Masaki Hashizume, Hiroyuki Yotsuyanagi

Proceedings of the 26th IEEE Asian Test Symposium, 2017

Open Defect Detection with a Built-in Test Circuit by IDDT Appearance Time in CMOS ICs.

Ayumu Kambara, Hiroyuki Yotsuyanagi, Daichi Miyoshi, Masaki Hashizume, Shyue-Kung Lu

Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016

A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs.

Widianto, Masaki Hashizume, Shohei Suenaga, Hiroyuki Yotsuyanagi, Akira Ono, Shyue-Kung Lu, Zvi Roth

IEICE Trans. Inf. Syst., 2016

2015

On TSV array defect detection method using two ring-oscillators considering signal transitions at adjacent TSVs.

Hiroyuki Yotsuyanagi, Akihiro Fujiwara, Masaki Hashizume

Proceedings of the 2015 International 3D Systems Integration Conference, 2015

Electrical interconnect test method of 3D ICs by injected charge volume.

Daisuke Suga, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu

Proceedings of the 2015 International 3D Systems Integration Conference, 2015

Electrical interconnect test of 3D ICs made of dies without ESD protection circuits with a built-in test circuit.

Kosuke Nanbara, Akihiro Odoriba, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu

Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014

A built-in supply current test circuit for electrical interconnect tests of 3D ICs.

Masaki Hashizume, Shoichi Umezu, Hiroyuki Yotsuyanagi, Shyue-Kung Lu

Proceedings of the 2014 International 3D Systems Integration Conference, 2014

2013

On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan.

Hiroyuki Yotsuyanagi, Hiroyuki Makimoto, Takanobu Nimiya, Masaki Hashizume

IEICE Trans. Inf. Syst., 2013

SAT-Based Test Generation for Open Faults Using Fault Excitation Caused by Effect of Adjacent Lines.

Jun Yamashita, Hiroyuki Yotsuyanagi, Masaki Hashizume, Kozo Kinoshita

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Testable Design for Electrical Testing of Open Defects at Interconnects in 3D ICs.

Masaki Hashizume, Tomoaki Konishi, Hiroyuki Yotsuyanagi, Shyue-Kung Lu

Proceedings of the 22nd Asian Test Symposium, 2013

2011

A supply current testable register string DAC of decoder type.

Masaki Hashizume, Yutaka Hata, Hiroyuki Yotsuyanagi, Yukiya Miura

Proceedings of the 11th International Symposium on Communications and Information Technologies, 2011

A Boundary Scan Circuit with Time-to-Digital Converter for Delay Testing.

Hiroyuki Yotsuyanagi, Hiroyuki Makimoto, Masaki Hashizume

Proceedings of the 20th IEEE Asian Test Symposium, 2011

A built-in test circuit for open defects at interconnects between dies in 3D ICs.

Widianto, Hiroyuki Yotsuyanagi, Akira Ono, Masao Takagi, Masaki Hashizume

Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

Supply current testing of open defects at interconnects in 3D Ics with IEEE 1149.1 architecture.

Tomoaki Konishi, Hiroyuki Yotsuyanagi, Masaki Hashizume

Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010

Scan Chain Ordering to Reduce Test Data for BIST-Aided Scan Test Using Compatible Scan Flip-Flops.

Hiroyuki Yotsuyanagi, Masayuki Yamamoto, Masaki Hashizume

IEICE Trans. Inf. Syst., 2010

Current-based testable design of level shifters in liquid crystal display drivers.

Masaki Hashizume, Kazuya Nakaminami, Hiroyuki Yotsuyanagi, Yukinori Nakajima, Kozo Kinoshita

Proceedings of the 15th European Test Symposium, 2010

Test Data Reduction for BIST-Aided Scan Test Using Compatible Flip-Flops and Shifting Inverter Code.

Masashi Ishikawa, Hiroyuki Yotsuyanagi, Masaki Hashizume

Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009

Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC.

Hiroyuki Yotsuyanagi, Masaki Hashizume, Toshiyuki Tsutsumi, Koji Yamazaki, Takashi Aikyo, Yoshinobu Higami, Hiroshi Takahashi, Yuzo Takamatsu

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

A Novel Approach for Improving the Quality of Open Fault Diagnosis.

Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

New Class of Tests for Open Faults with Considering Adjacent Lines.

Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi, Masaki Hashizume

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2007

Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines.

Hiroshi Takahashi, Yoshinobu Higami, Toru Kikkawa, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume

Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines.

Hiroshi Takahashi, Yoshinobu Higami, Shuhei Kadoyama, Takashi Aikyo, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi, Masaki Hashizume

Proceedings of the 16th Asian Test Symposium, 2007

Current Testable Design of Resistor String DACs.

Masaki Hashizume, Yutaka Hata, Tomomi Nishida, Hiroyuki Yotsuyanagi, Yukiya Miura

Proceedings of the 16th Asian Test Symposium, 2007

2006

Current Testable Design of Resistor String DACs.

Masaki Hashizume, Tomomi Nishida, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura

Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

A BIC Sensor Capable of Adjusting IDDQ Limit in Tests.

Masato Nakanishi, Masaki Hashizume, Hiroyuki Yotsuyanagi, Yukiya Miura

Proceedings of the 15th Asian Test Symposium, 2006

2005

Reducing Scan Shifts Using Configurations of Compatible and Folding Scan Trees.

Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita

J. Electron. Test., 2005

Electric field for detecting open leads in CMOS logic circuits by supply current testing.

Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

A test circuit for pin shorts generating oscillation in CMOS logic circuits.

Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada

Syst. Comput. Jpn., 2004

Test Sequence Generation for Test Time Reduction of IDDQ Testing.

Hiroyuki Yotsuyanagi, Masaki Hashizume, Takeomi Tamesada

IEICE Trans. Inf. Syst., 2004

Identification and Frequency Estimation of Feedback Bridging Faults Generating Logical Oscillation in CMOS Circuits.

Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada

IEICE Trans. Inf. Syst., 2004

On Configuring Scan Trees to Reduce Scan Shifts based on a Circuit Structure.

Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita

Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

Practical Fault Coverage of Supply Current Tests for Bipolar ICs.

Isao Tsukimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada

Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

CMOS Open Fault Detection by Appearance Time of Switching Supply Current.

Masaki Hashizume, Tetsuo Akita, Hiroyuki Yotsuyanagi, Takeomi Tamesada

Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

A Power Supply Circuit Recycling Charge in Adiabatic Dynamic CMOS Logic Circuits.

Daisuke Ezaki, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada

Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

I_DDQ Test Method Based on Wavelet Transformation for Noisy Current Measurement Environment.

Masaki Hashizume, Daisuke Yoneda, Hiroyuki Yotsuyanagi, Tetsuo Tada, Takeshi Koyama, Ikuro Morita, Takeomi Tamesada

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

Reducing Scan Shifts Using Folding Scan Trees.

Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

A BIST Circuit for IDDQ Tests.

Masaki Hashizume, Teppei Takeda, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura, Kozo Kinoshita

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

Random Pattern Testability of the Open Defect Detection Method using Application of Time-variable Electric Field.

Hiroyuki Yotsuyanagi, Masaki Hashizume, Taisuke Iwakiri, Masahiro Ichimiya, Takeomi Tamesada

Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

Power Supply Circuit for High Speed Operation of Adiabatic Dynamic CMOS Logic Circuits.

Masaki Hashizume, Masashi Sato, Hiroyuki Yotsuyanagi, Takeomi Tamesada

Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

Test Time Reduction for I DDQ Testing by Arranging Test Vectors.

Hiroyuki Yotsuyanagi, Masaki Hashizume, Takeomi Tamesada

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

Test Pattern for Supply Current Test of Open Defects by Applying Time-Variable Electric Field.

Hiroyuki Yotsuyanagi, Masaki Hashizume, Taisuke Iwakiri, Masahiro Ichimiya, Takeomi Tamesada

Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

CMOS open defect detection by supply current test.

Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Sequential Redundancy Removal Using Test Generation and Multiple Unreachable States.

Hiroyuki Yotsuyanagi, Shinsuke Hata, Masaki Hashizume, Takeomi Tamesada

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

IDDQ Sensing Technique for High Speed IDDQ Testing.

Teppei Takeda, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Yukiya Miura, Kozo Kinoshita

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

CMOS Open Defect Detection Based on Supply Current in Time-Variable Electric Field and Supply Voltage Application.

Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

Testability Analysis of IDDQ Testing with Large Threshold Value.

Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Masashi Takeda

Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

High speed IDDQ test and its testability for process variation.

Masaki Hashizume, Hiroyuki Yotsuyanagi, Masahiro Ichimiya, Takeomi Tamesada, Masashi Takeda

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

Identification of Feedback Bridging Faults with Oscillation.

Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998

Undetectable Fault Removal of Sequential Circuits Based on Unreachable States.

Hiroyuki Yotsuyanagi, Kozo Kinoshita

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

1997

Synthesis of Sequential Circuits by Redundancy Removal and Retiming.

Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita

J. Electron. Test., 1997

1995

Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement.

Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita

IEICE Trans. Inf. Syst., 1995

Resynthesis for sequential circuits designed with a specified initial state.

Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Synthesis for Testability by Sequential Redundancy Removal Using Retiming.

Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita

Proceedings of the Digest of Papers: FTCS-25, 1995