Hiroyuki Takenaka
According to our database1,
Hiroyuki Takenaka
authored at least 5 papers
between 1999 and 2008.
Collaborative distances:
Collaborative distances:
Timeline
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
0
1
2
1
1
1
1
1
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2001
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001
2000
A 0.5-μm, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor.
IEEE J. Solid State Circuits, 2000
1999
IEEE J. Solid State Circuits, 1999