Hiroyuki Morinaka

According to our database, Hiroyuki Morinaka authored at least 5 papers between 1996 and 1997.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1997

Authors Reply.

Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko

IEEE J. Solid State Circuits, 1997

Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply].

Vojin G. Oklobdzija, Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi

IEEE J. Solid State Circuits, 1997

1996

Leading-zero anticipatory logic for high-speed floating point addition.

Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi

IEEE J. Solid State Circuits, 1996

A 286 MHz 64-b floating point multiplier with enhanced CG operation.

Hiroshi Makino, Hiroaki Suzuki, Hiroyuki Morinaka, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi

IEEE J. Solid State Circuits, 1996

An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture.

Hiroshi Makino, Yasunobu Nakase, Hiroaki Suzuki, Hiroyuki Morinaka, Hirofumi Shinohara, Koichiro Mashiko

IEEE J. Solid State Circuits, 1996