Hiroyuki Kunishima
According to our database1,
Hiroyuki Kunishima
authored at least 3 papers
between 2005 and 2007.
Collaborative distances:
Collaborative distances:
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Bibliography
2007
Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS Generation.
IEICE Trans. Electron., 2007
2006
Chip-Level Performance Improvement Using Triple Damascene Wiring Design Concept for the 0.13 µm CMOS Generation and Beyond.
IEICE Trans. Electron., 2006
2005
Proceedings of the AMIA 2005, 2005