Hiroyuki Fukuyama
According to our database1,
Hiroyuki Fukuyama
authored at least 16 papers
between 1998 and 2021.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2021
A 15.1-mW 6-GS/s 6-bit Single-Channel Flash ADC With Selectively Activated 8× Time-Domain Latch Interpolation.
IEEE J. Solid State Circuits, 2021
2020
Design of a 45 Gb/s, 98 fJ/bit, 0.02 mm<sup>2</sup> Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS.
IEICE Trans. Electron., 2020
Proof of Authenticity of Logistics Information with Passive RFID Tags and Blockchain.
CoRR, 2020
2019
A 45 Gb/s, 98 fJ/bit, 0.02 mm<sup>2</sup> Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
2018
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018
A 15.1-mW 6-GS/s 6-bit Flash ADC with Selectively Activated 8× Time-Domain Interpolation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
A Low Input Referred Noise and Low Crosstalk Noise 25 Gb/s Transimpedance Amplifier with Inductor-Less Bandwidth Compensation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2016
An InP-Based 27-GHz-Bandwidth Limiting TIA IC Designed to Suppress Undershoot and Ringing in Its Output Waveform.
IEICE Trans. Electron., 2016
2014
400-G coherent receiver using silica-based heterogeneously-integrated PLC with newly developed waveplate type PBS.
Proceedings of the European Conference on Optical Communication, 2014
2012
Wide dynamic range transimpedance amplifier IC for 100-G DP-QPSK optical links using 1-µm InP HBTs.
IEICE Electron. Express, 2012
2011
Effects of Preamplifier Nonlinearity on PMD Equalization with Electronic Dispersion Compensation for 43G DQPSK.
IEICE Trans. Electron., 2011
2010
Study of a PMD Tolerance Extension by InP HBT Analog EDC IC without Adaptive Control in 43G DQPSK Transmission.
IEICE Trans. Electron., 2010
2004
A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector.
IEEE J. Solid State Circuits, 2004
IEEE J. Solid State Circuits, 2004
2001
A low-power direct digital synthesizer using a self-adjusting phase-interpolation technique.
IEEE J. Solid State Circuits, 2001
1998
Sampling phase detector using a resonant tunneling high electron mobility transistor for microwave phase-locked oscillators.
IEEE Trans. Very Large Scale Integr. Syst., 1998