Hiroto Yasuura

According to our database, Hiroto Yasuura authored at least 113 papers between 1981 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

ASP-DAC 2017 keynote speech I-3: Design of society: Beyond digital system design.

Hiroto Yasuura

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2012

A Selective Replacement Method for Timing-Error-Predicting flip-Flops.

Yuji Kunitake, Toshinori Sato, Hiroto Yasuura, Takanori Hayashida

J. Circuits Syst. Comput., 2012

Guidelines for mitigating NBTI degradation in on-chip memories.

Yuji Kunitake, Toshinori Sato, Hiroto Yasuura, Takanori Hayashida

Proceedings of the International Symposium on Communications and Information Technologies, 2012

Neutron-induced soft error rate estimation for SRAM using PHITS.

Shusuke Yoshimoto, Takuro Amashita, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

WiP Abstract: Estimation of Electric Power Consumption of Individuals by Observing People's Activity.

Atsushi Shimada, Shigeru Takano, Shigeaki Tagashira, Rin-Ichiro Taniguchi, Hiroto Yasuura

Proceedings of the 2012 IEEE/ACM Third International Conference on Cyber-Physical Systems, 2012

2011

Password Based Anonymous Authentication with Private Information Retrieval.

Toru Nakamura, Shunsuke Inenaga, Daisuke Ikeda, Kensuke Baba, Hiroto Yasuura

J. Digit. Inf. Manag., 2011

Towards Modeling Stored-value Electronic Money Systems.

Shunsuke Inenaga, Kenichirou Oyama, Hiroto Yasuura

Inf. Media Technol., 2011

Short Term Cell-Flipping Technique for Mitigating SNM Degradation Due to NBTI.

Yuji Kunitake, Toshinori Sato, Hiroto Yasuura

IEICE Trans. Electron., 2011

Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure.

Shusuke Yoshimoto, Takuro Amashita, D. Kozuwa, Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

An Anonymous Authentication Protocol with Single-database PIR.

Toru Nakamura, Shunsuke Inenaga, Kensuke Baba, Daisuke Ikeda, Hiroto Yasuura

Proceedings of the Ninth Australasian Information Security Conference, 2011

2010

Code and Data Placement for Embedded Processors with Scratchpad and Cache Memories.

Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura

J. Signal Process. Syst., 2010

An RTOS in hardware for energy efficient software-based TCP/IP processing.

Naotaka Maruyama, Tohru Ishihara, Hiroto Yasuura

Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010

A Replacement Strategy for Canary Flip-Flops.

Yuji Kunitake, Toshinori Sato, Hiroto Yasuura

Proceedings of the 16th IEEE Pacific Rim International Symposium on Dependable Computing, 2010

Signal probability control for relieving NBTI in SRAM cells.

Yuji Kunitake, Toshinori Sato, Hiroto Yasuura

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

An Identifiable Yet Unlinkable Authentication System with Smart Cards for Multiple Services.

Toru Nakamura, Shunsuke Inenaga, Daisuke Ikeda, Kensuke Baba, Hiroto Yasuura

Proceedings of the Computational Science and Its Applications, 2010

An Information Platform for Low-Literate Villagers.

Ashir Ahmed, Lutfe Kabir, Hiroto Yasuura

Proceedings of the 24th IEEE International Conference on Advanced Information Networking and Applications, 2010

2009

Single-Cycle-Accessible Two-Level Caches and Compilation Technique for Energy Reducion.

Seiichiro Yamaguchi, Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura

IPSJ Trans. Syst. LSI Des. Methodol., 2009

An Optimization Technique for Low-Energy Embedded Memory Systems.

Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura

IPSJ Trans. Syst. LSI Des. Methodol., 2009

Enhancements of a Circuit-Level Timing Speculation Technique and Their Evaluations Using a Co-simulation Environment.

Yuji Kunitake, Kazuhiro Mima, Toshinori Sato, Hiroto Yasuura

IEICE Trans. Electron., 2009

Modeling Costs of Access Control with Various Key Management Systems.

Tomomi Yamasaki, Shunsuke Inenaga, Daisuke Ikeda, Hiroto Yasuura

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2009

Large Scale Business-academia Collaboration in Master Education Course.

Noriaki Sakamoto, Mitsuaki Fukase, Tsunenori Mine, Shigeru Kusakabe, Tsuneo Nakanishi, Yoichi Omori, Mohammad Mesbah Uddin, Keijiro Araki, Akira Fukuda, Hiroto Yasuura, Teruaki Kitasuka

Proceedings of the CSEDU 2009 - Proceedings of the First International Conference on Computer Supported Education, Lisboa, Portugal, March 23-26, 2009, 2009

Dependable VLSI: device, design and architecture: how should they cooperate?

Shuichi Sakai, Hidetoshi Onodera, Hiroto Yasuura, James C. Hoe

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

A software technique to improve lifetime of caches containing ultra-leaky SRAM cells caused by within-die V_th variation.

Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura

Microelectron. J., 2008

A Multi-Application Smart Card System with Authentic Post-Issuance Program Modification.

Mohammad Mesbah Uddin, Yasunobu Nohara, Daisuke Ikeda, Hiroto Yasuura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

A Note on Biometrics-based Authentication with Portable Device.

Shinsuke Ohtsuka, Satoshi Kawamoto, Shigeru Takano, Kensuke Baba, Hiroto Yasuura

Proceedings of the SECRYPT 2008, 2008

Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption.

Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

A Framework of Authentic Post-Issuance Program Modification for Multi-Application Smart Cards.

Mohammad Mesbah Uddin, Salahuddin Muhammad Salim Zabir, Yasunobu Nohara, Hiroto Yasuura

Proceedings of the 2008 International Conference on Wireless Networks, 2008

Simultaneous optimization of memory configuration and code allocation for low power embedded systems.

Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

A Secure High-Speed Identification Scheme for RFID Using Bloom Filters.

Yasunobu Nohara, Sozo Inoue, Hiroto Yasuura

Proceedings of the The Third International Conference on Availability, 2008

2007

A low complexity and energy efficient dynamic channel allocation algorithm for multiuser OFDM.

Adil El Bourichi, Hiroto Yasuura

Proceedings of the Wireless Telecommunications Symposium, 2007

Unlinkability and Real World Constraints in RFID Systems.

Yasunobu Nohara, Sozo Inoue, Hiroto Yasuura

Proceedings of the Fifth Annual IEEE International Conference on Pervasive Computing and Communications, 2007

A Door Access Control System with Mobile Phones.

Tomomi Yamasaki, Toru Nakamura, Kensuke Baba, Hiroto Yasuura

Proceedings of the Personal Wireless Communications, 2007

Code Placement for Reducing the Energy Consumption of Embedded Processors with Scratchpad and Cache Memories.

Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura

Proceedings of the 2007 5th Workshop on Embedded Systems for Real-Time Multimedia, 2007

A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation.

Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Unlinkable Identification for Large-scale RFID Systems.

Yasunobu Nohara, Toru Nakamura, Kensuke Baba, Sozo Inoue, Hiroto Yasuura

Inf. Media Technol., 2006

On Authentication between Human and Computer.

Takahiro Watanabe, Yasunobu Nohara, Kensuke Baba, Sozo Inoue, Hiroto Yasuura

Proceedings of the 4th IEEE Conference on Pervasive Computing and Communications Workshops (PerCom 2006 Workshops), 2006

An Energy Characterization Framework for Software-Based Embedded Systems.

Donghoon Lee, Tohru Ishihara, Masanori Muroyama, Hiroto Yasuura, Farzan Fallah

Proceedings of the 2006 4th Workshop on Embedded Systems for Real-Time Multimedia, 2006

Systematic Error Detection for RFID Reliability.

Sozo Inoue, Hiroto Yasuura, Daisuke Hagiwara

Proceedings of the The First International Conference on Availability, 2006

2005

Special Section on Papers Selected from AP-ASIC 2004.

Hiroto Yasuura, Shoji Kawahito

IEICE Trans. Electron., 2005

Bitwidth Optimization for Low Power Digital FIR Filter Design.

Kosuke Tarumi, Akihiko Hyodo, Masanori Muroyama, Hiroto Yasuura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Quantitative evaluation of unlinkable ID matching schemes.

Yasunobu Nohara, Sozo Inoue, Kensuke Baba, Hiroto Yasuura

Proceedings of the 2005 ACM Workshop on Privacy in the Electronic Society, 2005

Toward Unlinkable ID Management for Multi-Service Environments.

Yasunobu Nohara, Sozo Inoue, Hiroto Yasuura

Proceedings of the 3rd IEEE Conference on Pervasive Computing and Communications Workshops (PerCom 2005 Workshops), 2005

A variation-aware low-power coding methodology for tightly coupled buses.

Masanori Muroyama, Kosuke Tarumi, Koji Makiyama, Hiroto Yasuura

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

An RFID-based multi-service system for supporting conference events.

Takahiro Watanabe, Sozo Inoue, Hiroto Yasuura, Jun Sasaki, Yasushi Aoki, Kazumi Akimoto

Proceedings of the 2005 International Conference on Active Media Technology, 2005

2004

Digitally Named World: Challenges for New Social Infrastructures.

Hiroto Yasuura

Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

2003

Reduction of coupling effects by optimizing the 3-D configuration of the routing grid.

Atsushi Sakai, Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura

IEEE Trans. Very Large Scale Integr. Syst., 2003

Routing Methodology for Minimizing Crosstalk in SoC.

Takashi Yamada, Atsushi Sakai, Yoshifumi Matsushita, Hiroto Yasuura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

Pre-Route Power Analysis Techniques for SoC.

Takashi Yamada, Takeshi Sakamoto, Shinji Furuichi, Mamoru Mukuno, Yoshifumi Matsushita, Hiroto Yasuura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

Variable Pipeline Depth Processor for Energy Efficient Systems.

Akihiko Hyodo, Masanori Muroyama, Hiroto Yasuura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

Leakage Power Reduction for Battery-Operated Portable Systems.

Yun Cao, Hiroto Yasuura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

Routing methodology for minimizing 1nterconnect energy dissipation.

Atsushi Sakai, Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura

Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Towards the Digitally Named World -Challenges for New Social Infrastructures based on Information Technologies.

Hiroto Yasuura

Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

A Power Reduction Scheme for Data Buses by Dynamic Detection of Active Bits.

Masanori Muroyama, Akihiko Hyodo, Takanori Okuma, Hiroto Yasuura

Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

Reduction of crosstalk noise by optimizing 3-D configuration of the routing grid.

Atsushi Sakai, Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Quality-driven design by bitwidth optimization for video applications.

Yun Cao, Hiroto Yasuura

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Quality-Driven Design for Video Applications.

Yun Cao, Hiroto Yasuura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

Optimization of Test Accesses with a Combined BIST and External Test Scheme.

Makoto Sugihara, Hiroto Yasuura

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

A Power Minimization Technique for Arithmetic Circuits by Cell Selection.

Masanori Muroyama, Tohru Ishihara, Akihiko Hyodo, Hiroto Yasuura

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Special Session: Security on SoC.

Hiroto Yasuura, Naofumi Takagi, Srivaths Ravi, Michael Torla, Catherine H. Gebotys

Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Data Memory Design Considering Effective Bitwidth for Low-Energy Embedded Systems.

Hiroto Yasuura, Hiroyuki Tomiyama, Takanori Okuma, Yun Cao

Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded Systems.

Hiroto Yasuura, Yun Cao, Mohammad Mesbah Uddin

Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Power analysis techniques for SoC with improved wiring models.

Takeshi Sakamoto, Takashi Yamada, Mamoru Mukuno, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Reducing access energy of on-chip data memory considering active data bitwidth.

Takanori Okuma, Yun Cao, Masanori Muroyama, Hiroto Yasuura

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

A low-power digital matched filter for spread-spectrum systems.

Shoji Goto, Takashi Yamada, Norihisa Takayama, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

A Design for a Low-Power Digital Matched Filter Applicable to W-CDMA.

Shoji Goto, Takashi Yamada, Norihisa Takayarna, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura

Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

2001

A High-Performance, Pipelined, FPGA-Based Genetic Algorithm Machine.

Barry Shackleford, Greg Snider, Richard J. Carter, Etsuko Okushi, Mitsuhiro Yasuda, Katsuhiko Seo, Hiroto Yasuura

Genet. Program. Evolvable Mach., 2001

Software Energy Reduction Techniques for Variable-Voltage Processors.

Takanori Okuma, Hiroto Yasuura, Tohru Ishihara

IEEE Des. Test Comput., 2001

A system-level energy minimization approach using datapath width optimization.

Yun Cao, Hiroto Yasuura

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

2000

Editorial.

Hiroto Yasuura

Des. Autom. Embed. Syst., 2000

Flexible System LSI for Embedded Systems and Its Optimization Techniques.

Akihiko Inoue, Tohru Ishihara, Hiroto Yasuura

Des. Autom. Embed. Syst., 2000

Functional Redundancy for Dynamic Exploitation of Performance-Energy Consumption Trade-Offs.

Victor M. Goulart Ferreira, Hiroto Yasuura

Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

Variable size analysis and validation of computation quality.

Hajime Yamashita, Hiroto Yasuura, Eko Fajar, Yun Cao

Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000

An FPGA-based genetic algorithm machine (poster abstract).

Barry Shackleford, Etsuko Okushi, Mitsuhiro Yasuda, Hisao Koizumi, Katsuhiko Seo, Takashi Iwamoto, Hiroto Yasuura

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000

Analysis and Minimization of Test Time in a Combined BIST and External Test Approach.

Makoto Sugihara, Hiroto Yasuura, Hiroshi Date

Proceedings of the 2000 Design, 2000

A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors.

Tohru Ishihara, Hiroto Yasuura

Proceedings of the 2000 Design, 2000

A Bus Delay Reduction Technique Considering Crosstalk.

Kei Hirose, Hiroto Yasuura

Proceedings of the 2000 Design, 2000

One language or more?: how can we design an SoC at a system level?

Masaharu Imai, Gary Smith, Steven Schulz, Karen Bartleson, Daniel Gajski, Wolfgang Rosenstiel, Peter Flake, Hiroto Yasuura

Proceedings of ASP-DAC 2000, 2000

1999

Real-Time Task Scheduling for a Variable Voltage Processor.

Takanori Okuma, Tohru Ishihara, Hiroto Yasuura

Proceedings of the 12th International Symposium on System Synthesis, 1999

1998

Embedded System Design Using Soft-Core Processor and Valen-C.

Hiroto Yasuura, Hiroyuki Tomiyama, Akihiko Inoue, Eko Fajar

J. Inf. Sci. Eng., 1998

A novel test methodology for core-based system LSIs and a testing time minimization problem.

Makoto Sugihara, Hiroshi Date, Hiroto Yasuura

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Statistical Performance-Driven Module Binding in High-Level Synthesis.

Hiroyuki Tomiyama, Akihiko Inoue, Hiroto Yasuura

Proceedings of the 11th International Symposium on System Synthesis, 1998

Instruction Encoding Techniques for Area Minimization of Instruction ROM.

Takanori Okuma, Hiroyuki Tomiyama, Akihiko Inoue, Eko Fajar, Hiroto Yasuura

Proceedings of the 11th International Symposium on System Synthesis, 1998

Voltage scheduling problem for dynamically variable voltage processors.

Tohru Ishihara, Hiroto Yasuura

Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Instruction Scheduling for Power Reduction in Processor-Based System Design.

Hiroyuki Tomiyama, Tohru Ishihara, Akihiko Inoue, Hiroto Yasuura

Proceedings of the 1998 Design, 1998

Module Selection Using Manufacturing Information.

Hiroyuki Tomiyama, Hiroto Yasuura

Proceedings of the ASP-DAC '98, 1998

Power-Pro: Programmable Power Management Architecture.

Tohru Ishihara, Hiroto Yasuura

Proceedings of the ASP-DAC '98, 1998

1997

Code placement techniques for cache miss rate reduction.

Hiroyuki Tomiyama, Hiroto Yasuura

ACM Trans. Design Autom. Electr. Syst., 1997

A High-Performance Hardware Implementation of a Survival-Based Genetic Algorithm.

Barry Shackleford, Etsuko Okushi, Mitsuhiro Yasuda, Hisao Koizumi, Katsuhiko Seo, Takashi Iwamoto, Hiroto Yasuura

Proceedings of the Progress in Connectionist-Based Information Systems: Proceedings of the 1997 International Conference on Neural Information Processing and Intelligent Information Systems, 1997

Memory-CPU Size Optimization for Embedded System Designs.

Barry Shackleford, Mitsuhiro Yasuda, Etsuko Okushi, Hisao Koizumi, Hiroyuki Tomiyama, Hiroto Yasuura

Proceedings of the 34st Conference on Design Automation, 1997

A HW/SW co-design environment for multi-media equipments development using inverse problem.

Fumio Suzuki, Hisao Koizumi, M. Hiramine, K. Yamamoto, Hiroto Yasuura, K. Okino

Proceedings of the Fifth International Workshop on Hardware/Software Codesign, 1997

1996

On the Computational Power of Binary Decision Diagram with Redundant Variables.

Tetsuya Yamada, Hiroto Yasuura

Formal Methods Syst. Des., 1996

Size-Constrained Code Placement for Cache Miss Rate Reduction.

Hiroyuki Tomiyama, Hiroto Yasuura

Proceedings of the 9th International Symposium on System Synthesis, 1996

Basic experimentation on accuracy of power estimation for CMOS VLSI circuits.

Tohru Ishihara, Hiroto Yasuura

Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Optimal Code Placement of Embedded Software for Instruction Caches.

Hiroyuki Tomiyama, Hiroto Yasuura

Proceedings of the 1996 European Design and Test Conference, 1996

1995

Foreword.

Hiroto Yasuura

IEICE Trans. Inf. Syst., 1995

A Proposal for a Co-design Method in Control Systems Using Combination of Models.

Hisao Koizumi, Katsuhiko Seo, Fumio Suzuki, Yoshisuke Ohtsuru, Hiroto Yasuura

IEICE Trans. Inf. Syst., 1995

1994

Design Reuse: Fact or Fiction? (Panel).

Nikil D. Dutt, David Agnew, Raul Camposano, Antun Domic, Manfred Wiesel, Hiroto Yasuura

Proceedings of the 31st Conference on Design Automation, 1994

1993

A Micro-Vectorprocessor Architecture: Performance Modeling and Benchmarking.

Takashi Hashimoto, Kazuaki J. Murakami, Tetsuo Hironaka, Hiroto Yasuura

Proceedings of the 7th international conference on Supercomputing, 1993

1992

Design of data-path module generators from algorithmic representations.

Vasily G. Moshnyaga, Keikichi Tamaru, Hiroto Yasuura

Proceedings of the Synthesis for Control Dominated Circuits, 1992

1990

Formal semantics of UDL/I and its applications to CAD/DA tools.

Hiroto Yasuura, Nagisa Ishiura

Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

Extraction of Functional Information from Combinatorial Circuits.

M. Ohmura, Hiroto Yasuura, Keikichi Tamaru

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

NES: The Behavioral Model for the Formal Semantics of a Hardware Design Language UDL/I.

Nagisa Ishiura, Hiroto Yasuura, Shuzo Yajima

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989

Semantics of a Hardware Design Language for Japanese Standardization.

Hiroto Yasuura, Nagisa Ishiura

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

Locally Computable Coding for Unary Operations.

Hiroto Yasuura

Proceedings of the Concurrency: Theory, 1989

1987

High-Speed Logic Simulation on Vector Processors.

Nagisa Ishiura, Hiroto Yasuura, Shuzo Yajima

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

On high-speed parallel algorithms using redundant coding.

Hiroto Yasuura, Naofumi Takagi, Shuzo Yajima

Syst. Comput. Jpn., 1987

1985

High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree.

Naofumi Takagi, Hiroto Yasuura, Shuzo Yajima

IEEE Trans. Computers, 1985

1984

Hardware Algorithms for VLSI Systems.

Hiroto Yasuura, Shuzo Yajima

Proceedings of the VLSI Engineering: Beyond Software Engineering, 1984

On Parallel Computational Complexity of Unification.

Hiroto Yasuura

Proceedings of the International Conference on Fifth Generation Computer Systems, 1984

1982

The Parallel Enumeration Sorting Scheme for VLSI.

Hiroto Yasuura, Naofumi Takagi, Shuzo Yajima

IEEE Trans. Computers, 1982

Hardware Algorithms and Logic Design Automation. An Overview and Progress Report.

Shuzo Yajima, Hiroto Yasuura

Proceedings of the RIMS Symposium on Software Science and Engineering, 1982

An Interactive Simulation System for structured logic design - ISS.

Takeshi Sakai, Yoshiyuki Tsuchida, Hiroto Yasuura, Yasushi Ooi, Yoshitsugu Ono, Hiroshi Kano, Shinji Kimura, Shuzo Yajima

Proceedings of the 19th Design Automation Conference, 1982

1981

Width and Depth of Combinational Logic Circuits.

Hiroto Yasuura

Inf. Process. Lett., 1981