Hirotaka Tamura
Orcid: 0000-0002-4152-1406
According to our database1,
Hirotaka Tamura
authored at least 81 papers
between 1998 and 2024.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2013, "For contributions to technology for high speed interconnects".
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
IEEE Access, 2024
IEEE Access, 2024
Digital Annealing Engine for High-speed Solving of Constrained Binary Quadratic Problems on Multiple GPUs.
Proceedings of the IEEE International Conference on Consumer Electronics, 2024
2023
Stat. Comput., December, 2023
Generating gradients in the energy landscape using rectified linear type cost functions for efficiently solving 0/1 matrix factorization in Simulated Annealing.
CoRR, 2023
CoRR, 2023
Efficient correlation-based discretization of continuous variables for annealing machines.
CoRR, 2023
2022
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022
2021
2020
Replica Exchange MCMC Hardware With Automatic Temperature Selection and Parallel Trial.
IEEE Trans. Parallel Distributed Syst., 2020
A Permutational Boltzmann Machine with Parallel Tempering for Solving Combinatorial Optimization Problems.
Proceedings of the Parallel Problem Solving from Nature - PPSN XVI, 2020
Proceedings of the 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2020
Digital Annealer for High-Speed Solving of Combinatorial optimization Problems and Its Applications.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2018
IEEE J. Solid State Circuits, 2018
IEEE J. Solid State Circuits, 2018
Physics-inspired optimization for constraint-satisfaction problems using a digital annealer.
CoRR, 2018
2017
A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS.
IEEE J. Solid State Circuits, 2017
Fast algorithm using summed area tables with unified layer performing convolution and average pooling.
Proceedings of the 27th IEEE International Workshop on Machine Learning for Signal Processing, 2017
6.6 A 22.5-to-32Gb/s 3.2pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the Complex, Intelligent, and Software Intensive Systems, 2017
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
2016
A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs.
IEEE J. Solid State Circuits, 2015
IEEE J. Solid State Circuits, 2015
25.78-Gb/s VCSEL-based optical transceiver with retimer-embedded driver and receiver ICs.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015
22.8 A 24-to-35Gb/s x4 VCSEL driver IC with multi-rate referenceless CDR in 0.13um SiGe BiCMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Proceedings of the Symposium on VLSI Circuits, 2014
On-chip measurement of data jitter with sub-picosecond accuracy for 10Gb/s multilane CDRs.
Proceedings of the Symposium on VLSI Circuits, 2014
A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution.
Proceedings of the Symposium on VLSI Circuits, 2014
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process.
IEEE J. Solid State Circuits, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2011
IEEE J. Solid State Circuits, 2011
A 60-GHz Injection-Locked Frequency Divider Using Multi-Order <i>LC</i> Oscillator Topology for Wide Locking Range.
IEICE Trans. Electron., 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
IEEE J. Solid State Circuits, 2010
IEEE J. Solid State Circuits, 2010
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
IEICE Trans. Electron., 2010
A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
A 60-GHz 1.65mW 25.9% locking range multi-order LC oscillator based injection locked frequency divider in 65nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
A combined anti-aliasing filter and 2-tap FFE in 65-nm CMOS for 2× blind 2-;10 Gb/s ADC-based receivers.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2009
IEEE J. Solid State Circuits, 2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2008
Event-Driven Modeling of CDR Jitter Induced by Power-Supply Noise, Finite Decision-Circuit Bandwidth, and Channel ISI.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
IEEE J. Solid State Circuits, 2008
2007
A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11-µm CMOS.
IEEE J. Solid State Circuits, 2007
IEEE J. Solid State Circuits, 2007
IEEE J. Solid State Circuits, 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2006
IEICE Trans. Electron., 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
2005
IEEE J. Solid State Circuits, 2005
IEEE J. Solid State Circuits, 2005
IEEE J. Solid State Circuits, 2005
A 0.8-1.3V 16-channel 2.5Gb/s high-speed serial transceiver in a 90nm standard CMOS process.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2003
1998
IEEE J. Solid State Circuits, 1998