Hiroshige Hirano

According to our database, Hiroshige Hirano authored at least 4 papers between 1997 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

Foreword.

Hiroshige Hirano

IEICE Trans. Electron., October, 2022

2005

A 0.9-V 1T1C SBT-based embedded nonvolatile FeRAM with a reference voltage scheme and multilayer shielded bit-line structure.

Kunisato Yamaoka, Shunichi Iwanari, Yasuo Murakuki, Hiroshige Hirano, Masahiko Sakagami, Tetsuji Nakakuma, Takashi Miki, Yasushi Gohou

IEEE J. Solid State Circuits, 2005

1999

FeRAM Circuit Technology for System on a Chip.

Koji Asari, Yukio Mitsuyama, Takao Onoye, Isao Shirakawa, Hiroshige Hirano, Toshiyuki Honda, Tatsuo Otsuki, Takaaki Baba, Teresa H. Meng

Proceedings of the 1st NASA / DoD Workshop on Evolvable Hardware (EH '99), 1999

1997

2-V/100-ns 1T/1C nonvolatile ferroelectric memory architecture with bitline-driven read scheme and nonrelaxation reference cell.

Hiroshige Hirano, Toshiyuki Honda, Nobuyuki Moriwaki, Tetsuji Nakakuma, Atsuo Inoue, George Nakane, Shigeo Chaya, Tatsumi Sumi

IEEE J. Solid State Circuits, 1997