Hiroshi Toyoshima

According to our database, Hiroshi Toyoshima authored at least 6 papers between 1992 and 1995.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1995

A 300-MHz 4-Mb wave-pipeline CMOS SRAM using a multiphase PLL.

Koichiro Ishibashi, Kunihiro Komiyaji, Hiroshi Toyoshima, Masataka Minami, Nagatoshi Ohki, Hiroshi Ishida, Toshiaki Yamanaka, Takahiro Nagano, Takashi Nishida

IEEE J. Solid State Circuits, November, 1995

A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers.

Koichiro Ishibashi, Koichi Takasugi, Kunihiro Komiyaji, Hiroshi Toyoshima, Toshiaki Yamanaka, Akira Fukami, Naotaka Hashimoto, Nagatoshi Ohki, Akihiro Shimizu, Takashi Hashimoto, Takahiro Nagano, Takashi Nishida

IEEE J. Solid State Circuits, April, 1995

1993

A 16-Mb CMOS SRAM with a 2.3- mu m² single-bit-line memory cell.

Katsuro Sasaki, Kiyotsugu Ueda, Koichi Takasugi, Hiroshi Toyoshima, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Nagatoshi Ohki

IEEE J. Solid State Circuits, November, 1993

1992

A 7-ns 140-mW 1-Mb CMOS SRAM with current sense amplifier.

Katsuro Sasaki, Koichiro Ishibashi, Kiyotsugu Ueda, Kunihiro Komiyaji, Toshiaki Yamanaka, Naotaka Hashimoto, Hiroshi Toyoshima, Fumio Kojima, Akihiro Shimizu

IEEE J. Solid State Circuits, November, 1992

A voltage down converter with submicroampere standby current for low-power static RAMs.

Koichiro Ishibashi, Katsuro Sasaki, Hiroshi Toyoshima

IEEE J. Solid State Circuits, June, 1992

A 1.7-V adjustable I/O interface for low-voltage fast SRAMs.

Koichiro Ishibashi, Katsuro Sasaki, Toshiaki Yamanaka, Hiroshi Toyoshima, Fumio Kojima

IEEE J. Solid State Circuits, April, 1992