Hiroshi Teramoto
According to our database1,
Hiroshi Teramoto
authored at least 8 papers
between 2011 and 2021.
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Bibliography
2021
Minor-embedding heuristics for large-scale annealing processors with sparse hardware graphs of up to 102, 400 nodes.
Soft Comput., 2021
STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions.
IEEE J. Solid State Circuits, 2021
2020
7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
Parametric standard system for mixed module and its application to singularity theory.
Proceedings of the ISSAC '20: International Symposium on Symbolic and Algebraic Computation, 2020
2018
Graph Minors from Simulated Annealing for Annealing Machines with Sparse Connectivity.
Proceedings of the Theory and Practice of Natural Computing - 7th International Conference, 2018
FPGA-Based QBoost with Large-Scale Annealing Processor and Accelerated Hyperparameter Search.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018
2011