Hiroshi Sasaki

Orcid: 0000-0001-7221-0742

Affiliations:

Tokyo Institute of Technology, Japan
Columbia University, NY, USA (former)
Kyushu University (former)
The University of Tokyo, Japan (former)

According to our database¹, Hiroshi Sasaki authored at least 33 papers between 2005 and 2021.

Collaborative distances:

Dijkstra number² of three.
Erdős number³ of three.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Bibliography

2021

RAPLET: Demystifying Publish/Subscribe Latency for ROS Applications.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2021

2019

Practical Byte-Granular Memory Blacklisting using Califorms.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

2018

Advances in Heterogeneous Computing from Hardware to Software (NII Shonan Meeting 2018-11).

[BibT_eX]

[DOI]

Aaron Smith

Chris Fensch

Hiroshi Sasaki

NII Shonan Meet. Rep., 2018

Evaluating Energy-Efficiency of DRAM Channel Interleaving Schemes for Multithreaded Programs.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2018

2017

Enhanced Dependence Graph Model for Critical Path Analysis on Modern Out-of-Order Processors.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2017

Heavy Tails in Program Structure.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2017

Mitigating Power Contention: A Scheduling Based Approach.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2017

Why do programs have heavy tails?

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017

2016

A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2016

Power-Efficient Breadth-First Search with DRAM Row Buffer Locality-Aware Address Mapping.

[BibT_eX]

[DOI]

Proceedings of the 2016 High Performance Graph Data Management and Processing Workshop, 2016

A Scalability Analysis of Many Cores and On-Chip Mesh Networks on the TILE-Gx Platform.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

Characterization and mitigation of power contention across multiprogrammed workloads.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on Workload Characterization, 2016

2015

Runtime multi-optimizations for energy efficient on-chip interconnections1.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

A flexible hardware barrier mechanism for many-core processors.

[BibT_eX]

[DOI]

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

Power and Performance Characterization and Modeling of GPU-Accelerated Systems.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE 28th International Parallel and Distributed Processing Symposium, 2014

Power-capped DVFS and thread allocation with ANN models on modern NUMA systems.

[BibT_eX]

[DOI]

Satoshi Imamura

Hiroshi Sasaki

Koji Inoue

Dimitrios S. Nikolopoulos

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013

Predict-More Router: A Low Latency NoC Router with More Route Predictions.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Power and performance of GPU-accelerated systems: A closer look.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Workload Characterization, 2013

Line sharing cache: Exploring cache capacity with frequent line value locality.

[BibT_eX]

[DOI]

Keitarou Oka

Hiroshi Sasaki

Koji Inoue

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

SMYLEref: A reference architecture for manycore-processor SoCs.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Coordinated power-performance optimization in manycores.

[BibT_eX]

[DOI]

Hiroshi Sasaki

Satoshi Imamura

Koji Inoue

Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013

McRouter: Multicast within a router for high performance network-on-chips.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013

2012

Geyser.

[BibT_eX]

[DOI]

Proceedings of the Handbook of Energy-Aware and Green Computing - Two Volume Set., 2012

Adaptive Data Compression on 3D Network-on-Chips.

[BibT_eX]

[DOI]

Inf. Media Technol., 2012

Power and Performance Analysis of GPU-Accelerated Systems.

[BibT_eX]

[DOI]

Proceedings of the 2012 Workshop on Power-Aware Computing Systems, HotPower'12, 2012

Scalability-based manycore partitioning.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011

Performance evaluation of 3D stacked multi-core processors with temperature consideration.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2009

Energy-Efficient Dynamic Instruction Scheduling Logic Through Instruction Grouping.

[BibT_eX]

[DOI]

Hiroshi Sasaki

Masaaki Kondo

Hiroshi Nakamura

IEEE Trans. Very Large Scale Integr. Syst., 2009

Cooperative shared resource access control for low-power chip multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Power-performance modeling of heterogeneous cluster-based web servers.

[BibT_eX]

[DOI]

Proceedings of the 2009 10th IEEE/ACM International Conference on Grid Computing, 2009

2007

Improving fairness, throughput and energy-efficiency on a chip multiprocessor through DVFS.

[BibT_eX]

[DOI]

Masaaki Kondo

Hiroshi Sasaki

Hiroshi Nakamura

SIGARCH Comput. Archit. News, 2007

An intra-task dvfs technique based on statistical analysis of hardware events.

[BibT_eX]

[DOI]

Proceedings of the 4th Conference on Computing Frontiers, 2007

2005

Dynamic Instruction Cascading on GALS Microprocessors.

[BibT_eX]

[DOI]

Hiroshi Sasaki

Masaaki Kondo

Hiroshi Nakamura

Proceedings of the Integrated Circuit and System Design, 2005

Hiroshi Sasaki

Timeline

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