Hiroshi Onoda

According to our database, Hiroshi Onoda authored at least 7 papers between 1994 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

Visual Identification-Based Spark Recognition System.

Tianhao Cheng, Hao Hu, Hitoshi Kobayashi, Hiroshi Onoda

Int. J. Autom. Technol., 2022

Readiness Status of Artificial Intelligence Applications on Electric Vehicles: A mini global review and analysis using the J-TRA method.

Andante Hadi Pandyaswargo, Meilinda Fitriani Nur Maghfiroh, Hiroshi Onoda

Proceedings of the International Conference on Engineering and Information Technology for Sustainable Industry, 2022

2020

Environmental and Economic Evaluation of a Mechanical Biological Treatment System for a Small and Medium-Sized Waste Treatment Facility Considering the Karatsu Smart Disaster-Resilience Base Construction Project.

Akihisa Ogawa, Andante Hadi Pandyaswargo, Daiki Yoshidome, Hiroshi Onoda

Int. J. Autom. Technol., 2020

2013

0.5 V Start-Up 87% Efficiency 0.75 mm² On-Chip Feed-Forward Single-Inductor Dual-Output (SIDO) Boost DC-DC Converter for Battery and Solar Cell Operation Sensor Network Micro-Computer Integration.

Yasunobu Nakase, Shinichi Hirose, Hiroshi Onoda, Yasuhiro Ido, Yoshiaki Shimizu, Tsukasa Oishi, Toshio Kumamoto, Toru Shimizu

IEEE J. Solid State Circuits, 2013

2012

A 0.5V start-up 87% efficiency 0.75mm² on-chip feed-forward single-inductor dual-output (SIDO) boost DC-DC converter for battery and solar cell operation sensor network micro-computer integration.

Yasunobu Nakase, Shinichi Hirose, Hiroshi Onoda, Yasuhiro Ido, Yoshiaki Shimizu, Tsukasa Oishi, Toshio Kumamoto, Toru Shimizu

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011

0.8V start-up 92% efficiency on-chip boost DC-DC converters for battery operation micro-computers.

Yasunobu Nakase, Shinichi Hirose, Toru Goda, Kehui Hu, Hiroshi Onoda, Yasuhiro Ido, Hiroyuki Kondo, Wei Kong, Wei Zhang, Tsukasa Oishi, Shintaro Mori, Toru Shimizu

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

1994

Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory.

Shin'ichi Kobayashi, Hiroaki Nakai, Yuichi Kunori, Takeshi Nakayama, Yoshikazu Miyawaki, Yasushi Terada, Hiroshi Onoda, Natsuo Ajika, Masahiro Hatanaka, Hirokazu Miyoshi, Tsutomu Yoshihara

IEEE J. Solid State Circuits, April, 1994