Hiroshi Nakayama
According to our database1,
Hiroshi Nakayama
authored at least 10 papers
between 1999 and 2024.
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Bibliography
2024
Digital Annealing Engine for High-speed Solving of Constrained Binary Quadratic Problems on Multiple GPUs.
Proceedings of the IEEE International Conference on Consumer Electronics, 2024
2016
Proceedings of the International Conference on Machine Learning and Cybernetics, 2016
Proceedings of the 2016 IEEE International Conference on Fuzzy Systems, 2016
2015
Computer-aided Surgical Planning of Anterior Cruciate Ligament Reconstruction in MR Images.
Proceedings of the 19th International Conference in Knowledge Based and Intelligent Information and Engineering Systems, 2015
2012
Proceedings of the IEEE International Conference on Consumer Electronics, 2012
2010
IEICE Electron. Express, 2010
Signal-integrity improvement method and its robustness evaluation for VLSI and VLSI-packaging.
Artif. Life Robotics, 2010
A novel hardware-friendly self-adjustable offset min-sum algorithm for ISDB-S2 LDPC decoder.
Proceedings of the 18th European Signal Processing Conference, 2010
2008
Proceedings of the Evolvable Systems: From Biology to Hardware, 2008
1999
A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry processor with SIMD instructions and a software bypass mechanism.
IEEE J. Solid State Circuits, 1999