Hiroshi Miyashita

According to our database1, Hiroshi Miyashita authored at least 16 papers between 1986 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
Designing Researchmap: A Revolutionary Scholar Support Platform Achieved Through Human-AI Collaboration.
Proceedings of the 6th IEEE International Conference on Knowledge Innovation and Invention, 2023

2021
Human-centric data protection laws and policies: A lesson from Japan.
Comput. Law Secur. Rev., 2021

MN-Core - A Highly Efficient and Scalable Approach to Deep Learning.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

2017
Automated Historical Fact-Checking by Passage Retrieval, Word Statistics, and Virtual Question-Answering.
Proceedings of the Eighth International Joint Conference on Natural Language Processing, 2017

2016
NUL System at QA Lab-2 Task.
Proceedings of the 12th NTCIR Conference on Evaluation of Information Access Technologies, 2016

2014
NUL System at QALab Tasks.
Proceedings of the 11th NTCIR Conference on Evaluation of Information Access Technologies, 2014

NUL System at NTCIR RITE-VAL Tasks.
Proceedings of the 11th NTCIR Conference on Evaluation of Information Access Technologies, 2014

2013
Basis of monitoring central blood pressure and hemodynamic parameters by peripheral arterial pulse waveform analyses.
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013

2007
Efficient Thermal Via Planning for Placement of 3D Integrated Circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
Thermal-Aware Placement Based on FM Partition Scheme and Force-Directed Heuristic.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Post-placement Thermal Via Planning for 3D Integrated Circuit.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
Equidistance routing in high-speed VLSI layout design.
Integr., 2005

An Incremental Placement Algorithm for Building Block Layout Design Based on the O-Tree Representation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

2002
On the equivalence of the sequence pair for rectangle packing to the dimension of partial orders [floorplanning].
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

1995
Extending pitchmaking algorithms to layouts with multiple grid constraints.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1986
An automatic cell pattern generation system for CMOS transistor-pair array LSI.
Integr., 1986


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