Hiroshi Iwata

According to our database, Hiroshi Iwata authored at least 8 papers between 2010 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Verification and Validation with Prototype Chip Implemented with Layout Level Scan C-Elements.

Hiroshi Iwata, Kokoro Yamasaki, Ken-ichi Yamaguchi

J. Electron. Test., August, 2024

2017

Formal Verification-Based Redundancy Identification of Transition Faults with Broadside Scan Tests.

Hiroshi Iwata, Nanami Katayama, Ken-ichi Yamaguchi

IEICE Trans. Inf. Syst., 2017

2010

A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification.

Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara

IEICE Trans. Inf. Syst., 2010

Broadband robust PWM power amplifier using approximate 2DOF digital control.

Takahiro Nomura, Hiroshi Iwata, Kohji Higuchi, Kazushi Nakano

Artif. Life Robotics, 2010

Test pattern selection to optimize delay test quality with a limited size of test set.

Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata, Hideo Fujiwara

Proceedings of the 15th European Test Symposium, 2010

Enabling False Path Identification from RTL for Reducing Design and Test Futileness.

Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara

Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010

A synthesis method to propagate false path information from RTL to gate level.

Satoshi Ohtake, Hiroshi Iwata, Hideo Fujiwara

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Bipartite Full Scan Design: A DFT Method for Asynchronous Circuits.

Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara

Proceedings of the 19th IEEE Asian Test Symposium, 2010