Hiroshi Date

According to our database, Hiroshi Date authored at least 16 papers between 1990 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2021

Deformation analysis of surface and bronchial structures in intraoperative pneumothorax using deformable mesh registration.

Megumi Nakao, Kotaro Kobayashi, Junko Tokuno, Toyofumi Chen-Yoshikawa, Hiroshi Date, Tetsuya Matsuda

Medical Image Anal., 2021

2020

Statistical modeling of pneumothorax deformation by mapping CT and cone-beam CT images.

Megumi Nakao, Hinako Maekawa, Katsutaka Mineura, Toyofumi Chen-Yoshikawa, Hiroshi Date, Tetsuya Matsuda

CoRR, 2020

Analysis of Heterogeneity of Pneumothorax-associated Deformation using Model-based Registration.

Megumi Nakao, Kotaro Kobayashi, Junko Tokuno, Toyofumi Chen-Yoshikawa, Hiroshi Date, Tetsuya Matsuda

CoRR, 2020

2019

Surface deformation analysis of collapsed lungs using model-based shape matching.

Megumi Nakao, Junko Tokuno, Toyofumi Chen-Yoshikawa, Hiroshi Date, Tetsuya Matsuda

Int. J. Comput. Assist. Radiol. Surg., 2019

2008

Effects of At-Home Nursing Service Scheduling in Multiagent Systems.

Hiroshi Date, Tokuro Matsuo

Proceedings of the New Challenges in Applied Intelligence Technologies, 2008

2004

A DFT Selection Method for Reducing Test Application Time of System-on-Chips.

Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara

IEICE Trans. Inf. Syst., 2004

2003

A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint.

Toshinori Hosokawa, Hiroshi Date, Masahide Miyazaki, Michiaki Muraoka, Hideo Fujiwara

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits.

Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

A State Reduction Method for Non-Scan Based FSM Testing with Don't Care Inputs Identification Technique.

Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

A SoC Test Strategy Based on a Non-Scan DFT Method.

Hiroshi Date, Toshinori Hosokawa, Michiaki Muraoka

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2000

Mathematical Modeling of Intellectual Property Protection Using Partially-Mergeable Cores.

Hiroshi Date, Vikram Iyengar, Krishnendu Chakrabarty, Makoto Sugihara

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

Analysis and Minimization of Test Time in a Combined BIST and External Test Approach.

Makoto Sugihara, Hiroto Yasuura, Hiroshi Date

Proceedings of the 2000 Design, 2000

1998

A novel test methodology for core-based system LSIs and a testing time minimization problem.

Makoto Sugihara, Hiroshi Date, Hiroto Yasuura

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1995

A parallel sequential test generation system DESCARTES based on real-valued logic simulation.

Hiroshi Date, Michinobu Nakao, Kazumi Hatayama

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1992

LSI-CAD Programs on Parallel Inference Machine.

Hiroshi Date, Yukinori Matsumoto, Kouichi Kimura, Kazuo Taki, Hiroo Kato, Masahiro Hoshi

Proceedings of the International Conference on Fifth Generation Computer Systems. FGCS 1992, 1992

1990

LSI module placement methods using neural computation networks.

Hiroshi Date, Mitsuho Seki, Terumine Hayashi

Proceedings of the IJCNN 1990, 1990