Hiroomi Hikawa

Orcid: 0000-0003-2609-3500

According to our database1, Hiroomi Hikawa authored at least 70 papers between 1992 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
Electroencephalogram-Based Facial Gesture Recognition Using Self-Organizing Map.
Sensors, May, 2024

2023
A Survey of Hardware Self-Organizing Maps.
IEEE Trans. Neural Networks Learn. Syst., November, 2023

2021
Hardware Self-Organizing Map Based on Digital Frequency-Locked Loop and Triangular Neighborhood Function.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A Synthesis Method of Spiking Neural Oscillators with Considering Asymptotic Stability.
Proceedings of the International Joint Conference on Neural Networks, 2021

2020
Nested Pipeline Hardware Self-Organizing Map for High Dimensional Vectors.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

2019
Nested Hardware Architecture for Self-Organizing Map.
Proceedings of the International Joint Conference on Neural Networks, 2019

2018
SOM-Based Vector Recognition with Pre-Grouping Functionality.
IEICE Trans. Inf. Syst., 2018

A Subspace Newton-Type Method for Approximating Transversely Repelling Chaotic Saddles.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

Off-Chip Training with Additive Perturbation for FPGA-Based Hand Sign Recognition System.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

A New Self-Organizing Map with Continuous Learning Capability.
Proceedings of the IEEE Symposium Series on Computational Intelligence, 2018

Hardware Self-Organizing Map Based on Frequency-Modulated Signal and Digital Frequency-Locked Loop.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A New Hardware Self-Organizing Map Architecture with High Expandability.
Proceedings of the IEEE International Conference on Image Processing, 2018

2016
Effect of grouping in vector recognition system based on SOM.
Proceedings of the 2016 IEEE Symposium Series on Computational Intelligence, 2016

Real time gesture recognition system with gesture spotting function.
Proceedings of the 2016 IEEE Symposium Series on Computational Intelligence, 2016

Off-chip learning for hardware hand-sign recognition system.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Live demonstration: Off-chip learning for hardware hand-sign recognition system.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Gesture Spotting by Using Vector Distance of Self-organizing Map.
Proceedings of the Neural Information Processing - 23rd International Conference, 2016

Improved winner-take-all circuit for neural network based on frequency-modulated signals.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015
Improved Learning Performance of Hardware Self-Organizing Map Using a Novel Neighborhood Function.
IEEE Trans. Neural Networks Learn. Syst., 2015

Novel FPGA Implementation of Hand Sign Recognition System With SOM-Hebb Classifier.
IEEE Trans. Circuits Syst. Video Technol., 2015

Low-Power Wiring Method for Band-Limited Signals in CMOS Logic Circuits by Segmentation Coding with Pseudo-Majority Voting.
IEICE Trans. Electron., 2015

Scalable Hardware Winner-Take-All Neural Network with DPLL.
IEICE Trans. Inf. Syst., 2015

Winner-take-all neural network with digital frequency-locked loop.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Vector classification by a winner-take-all neural network with digital frequency-locked loop.
Proceedings of the 2015 International Joint Conference on Neural Networks, 2015

2014
Low-power wiring method in CMOS logics circuits by segmentation coding and pseudo majority voting.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Supervised learning of DPLL based winner-take-all neural network.
Proceedings of the 2014 IEEE International Conference on Evolvable Systems, 2014

2013
Color-space image compression with hardware Self-organizing map.
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2013

A new winner-take-all neural network using DPLL and phase modulated signal.
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2013

DPLL based hardware SOM with a new winner-take-all circuit.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013

2012
Sequential vector classifier based on SOM and feedback Hebbian network.
Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2012

Real time gesture recognition system using posture classifier and Jordan recurrent neural network.
Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), 2012

2011
ROM-Less Phase to Amplitude Converter Using Sine Wave Approximation Based on Harmonic Removal from Trapezoid Wave.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Hand sign recognition system based on SOM-Hebb hybrid network.
Proceedings of the IEEE International Conference on Systems, 2011

Automatic generation of hardware self-organizing map for FPGA implementation.
Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2011

Hardware design of a color quantization with self-organizing map.
Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2011

Study on gesture recognition system using posture classifier and Jordan recurrent neural network.
Proceedings of the 2011 International Joint Conference on Neural Networks, 2011

Learning Scheme for Complex Neural Networks Using Simultaneous Perturbation.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2011, 2011

2010
Phase amplitude converter with conditional shift operation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Comparison of range check classifier and hybrid network classifier for hand sign recognition system.
Proceedings of the International Joint Conference on Neural Networks, 2010

Image compression with hardware self-organizing map.
Proceedings of the International Joint Conference on Neural Networks, 2010

2009
Statistical Mechanical Analysis of Simultaneous Perturbation Learning.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

DDFS with New Sinusoid Approximation based on Harmonics Removal.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Hand sign recognition system based on hybrid network classifier.
Proceedings of the International Joint Conference on Neural Networks, 2009

On automatic generation of VHDL code for self-organizing map.
Proceedings of the International Joint Conference on Neural Networks, 2009

On simultaneous perturbation particle swarm optimization.
Proceedings of the IEEE Congress on Evolutionary Computation, 2009

2008
Hardware Design of Japanese Hand Sign Recognition System.
Proceedings of the Advances in Neuro-Information Processing, 15th International Conference, 2008

2007
Hardware Feedback Self-Organizing Map and its Application to Mobile Robot Location Identification.
J. Adv. Comput. Intell. Intell. Informatics, 2007

Performance Comparison of SOM Based Hybrid Hardware Classifiers.
Proceedings of the International Joint Conference on Neural Networks, 2007

Pseudo RBF Network for Position Independent Hand Posture Recognition System.
Proceedings of the International Joint Conference on Neural Networks, 2007

A New Hardware Friendly Vector Distance Evaluation Function for Vector Classifiers.
Proceedings of the Neural Information Processing, 14th International Conference, 2007

Japanese Hand Sign Recognition System.
Proceedings of the Neural Information Processing, 14th International Conference, 2007

2006
Vector Quantization System Based on Scalar SOM/AND-OR Hybrid Network.
Proceedings of the International Joint Conference on Neural Networks, 2006

2005
FPGA implementation of self organizing map with digital phase locked loops.
Neural Networks, 2005

Hardware friendly vector quantization algorithm.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Direct digital frequency synthesizer with multi-stage linear interpolation.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
A digital hardware pulse-mode neuron with piecewise linear activation function.
IEEE Trans. Neural Networks, 2003

A new digital pulse-mode neuron with adjustable activation function.
IEEE Trans. Neural Networks, 2003

A multilayer neural network with pulse position modulation.
Syst. Comput. Jpn., 2003

Pulse mode neuron with leakage integrator and additive random noise.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2001
Digital pulse mode neural network with simple synapse multiplier.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
An efficient three-valued multilayer neural network with on-chip learning suitable for hardware implementation.
Syst. Comput. Jpn., 2000

Pulse mode multilayer neural network based on floating point number representation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Pulse Mode Multilayer Neural Network with Floating Point Operation and On-Chip Learning.
Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks, 2000

1999
Frequency-based multilayer neural network with on-chip learning and enhanced neuron characteristics.
IEEE Trans. Neural Networks, 1999

Implementation of multilayer neural network with threshold neurons and its analysis.
Artif. Life Robotics, 1999

An efficient pulse mode multilayer neural network.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1995
Implementation of simplified multilayer neural networks with on-chip learning.
Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995

1994
Parallel Architecture for Universal Digital Signal Processing.
Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994

1992
A radix-8 wafer scale FFT processor.
J. VLSI Signal Process., 1992

An Architecture for WSI Rapid Prototyping.
Computer, 1992


  Loading...