Hiroo Masuda
According to our database1,
Hiroo Masuda
authored at least 31 papers
between 1985 and 2010.
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Bibliography
2010
A New LDMOS Transistor Macro-Modeling for Accurately Predicting Bias Dependence of Gate-Overlap Capacitance.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
IEICE Trans. Electron., 2010
2009
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
2008
A Novel Expression of Spatial Correlation by a Random Curved Surface Model and Its Application to LSI Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
Concise Modeling of Transistor Variations in an LSI Chip and Its Application to SRAM Cell Sensitivity Analysis.
IEICE Trans. Electron., 2008
2006
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
2005
A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
Design Guidelines and Process Quality Improvement for Treatment of Device Variations in an Lsi Chip.
IEICE Trans. Electron., 2005
Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2004
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
Crosstalk delay analysis of a 0.13-μm node test chip and precise gate-level simulation technology.
IEEE J. Solid State Circuits, 2003
Approximation Formula Approach for the Efficient Extraction of On-Chip Mutual Inductances.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
Design and Measurement of an Inductance-Oscillator for Analyzing Inductance Impact on On-Chip Interconnect Delay.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
1998
TCAD/DA for MPU and ASIC Development.
Proceedings of the ASP-DAC '98, 1998
1991
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991
1988
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988
1987
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987
1985
Three-Dimensional Device Simulator CADDETH with Highly Convergent Matrix Solution Algorithms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985