Hiromu Miyazaki

According to our database, Hiromu Miyazaki authored at least 5 papers between 2019 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2020

RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining.

Hiromu Miyazaki, Takuto Kanamori, Md. Ashraful Islam, Kenji Kise

IEICE Trans. Inf. Syst., 2020

RVCoreP-32IC: A high-performance RISC-V soft processor with an efficient fetch unit supporting the compressed instructions.

Takuto Kanamori, Hiromu Miyazaki, Kenji Kise

CoRR, 2020

RVCoreP-32IM: An effective architecture to implement mul/div instructions for five stage RISC-V soft processors.

Md. Ashraful Islam, Hiromu Miyazaki, Kenji Kise

CoRR, 2020

A portable and Linux capable RISC-V computer system in Verilog HDL.

Junya Miura, Hiromu Miyazaki, Kenji Kise

CoRR, 2020

2019

An Efficient Instruction Fetch Architecture for a RISC-V Soft Processor on an FPGA.

Hiromu Miyazaki, Junya Miura, Kenji Kise

Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2019