Hiromu Fujioka

According to our database1, Hiromu Fujioka authored at least 15 papers between 1996 and 2007.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Awards

IEEE Fellow

IEEE Fellow 2004, "For contributions to electron beam testing of semiconductor devices and circuits.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2007
Estimation of electron probe profile from SEM image through wavelet multiresolution analysis for inline SEM inspection.
Image Vis. Comput., 2007

Computer-assisted lesion detection system for stomach screening using stomach shape and appearance models.
Proceedings of the Medical Imaging 2007: Computer-Aided Diagnosis, 2007

2006
Image deblurring by the combined use of a super-resolution technique and inverse filtering.
Proceedings of the Computational Imaging IV, San Jose, 2006

2003
A low energy FIB processing, repair, and test system.
Microelectron. Reliab., 2003

Cost Optimum Embedded DRAM Design by Yield Analysis.
Proceedings of the 11th IEEE International Workshop on Memory Technology, 2003

2002
CAD navigation system, for backside waveform probing of CMOS devices.
Microelectron. Reliab., 2002

2001
Development of an EB/FIB Integrated Test System.
Microelectron. Reliab., 2001

2000
EB tester fault localization algorithm for combinational circuits by utilizing fault simulation and test pattern sequence for EB tester.
Syst. Comput. Jpn., 2000

1999
Intelligent EB Test System for Automatic VLSI Fault Tracing.
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998
Knowledge-based circuit recognition from standard-cell design CMOS VLSI optical microscope images.
Syst. Comput. Jpn., 1998

1997
Hierarchical VLSI Fault Tracing by Successive Circuit Extraction from CAD Layout Data in the CAD-Linked EB Test System.
J. Electron. Test., 1997

Automatic EB Fault Tracing System by Successive Circuit Extraction from VLSI CAD Layout Data.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

Hierarchical fault tracing for VLSI sequential circuits from CAD layout data in the CAD-linked EB test system.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996
How ATE Planning Affects LSI Manufacturing Cost.
IEEE Des. Test Comput., 1996

Effects of Multi-Product, Small-Sized Production of LSIs Packaged in Various Packages on the Final Test Process Efficiency and Cost.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996


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