Hiromu Fujioka

According to our database, Hiromu Fujioka authored at least 15 papers between 1996 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2007

Estimation of electron probe profile from SEM image through wavelet multiresolution analysis for inline SEM inspection.

Koji Nakamae, Masaki Chikahisa, Hiromu Fujioka

Image Vis. Comput., 2007

Computer-assisted lesion detection system for stomach screening using stomach shape and appearance models.

Yoshihiro Midoh, M. Nakamura, M. Takashima, Koji Nakamae, Hiromu Fujioka

Proceedings of the Medical Imaging 2007: Computer-Aided Diagnosis, San Diego, 2007

2006

Image deblurring by the combined use of a super-resolution technique and inverse filtering.

Yasuyuki Yamada, Koji Nakamae, Hiromu Fujioka

Proceedings of the Computational Imaging IV, San Jose, 2006

2003

A low energy FIB processing, repair, and test system.

Katsuyoshi Miura, Tomoyuki Kobatake, Koji Nakamae, Hiromu Fujioka

Microelectron. Reliab., 2003

Cost Optimum Embedded DRAM Design by Yield Analysis.

Youhei Zenda, Koji Nakamae, Hiromu Fujioka

Proceedings of the 11th IEEE International Workshop on Memory Technology, 2003

2002

CAD navigation system, for backside waveform probing of CMOS devices.

Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka

Microelectron. Reliab., 2002

2001

Development of an EB/FIB Integrated Test System.

Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka

Microelectron. Reliab., 2001

2000

EB tester fault localization algorithm for combinational circuits by utilizing fault simulation and test pattern sequence for EB tester.

Koji Nakamae, Takashi Ishimura, Hiromu Fujioka

Syst. Comput. Jpn., 2000

1999

Intelligent EB Test System for Automatic VLSI Fault Tracing.

Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998

Knowledge-based circuit recognition from standard-cell design CMOS VLSI optical microscope images.

Koji Nakamae, Shinji Yokoyama, Atsushi Onishi, Hiromu Fujioka

Syst. Comput. Jpn., 1998

1997

Hierarchical VLSI Fault Tracing by Successive Circuit Extraction from CAD Layout Data in the CAD-Linked EB Test System.

Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka

J. Electron. Test., 1997

Automatic EB Fault Tracing System by Successive Circuit Extraction from VLSI CAD Layout Data.

Katsuyoshi Miura, Kohei Nakata, Koji Nakamae, Hiromu Fujioka

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

Hierarchical fault tracing for VLSI sequential circuits from CAD layout data in the CAD-linked EB test system.

Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996

How ATE Planning Affects LSI Manufacturing Cost.

Koji Nakamae, Homare Sakamoto, Hiromu Fujioka

IEEE Des. Test Comput., 1996

Effects of Multi-Product, Small-Sized Production of LSIs Packaged in Various Packages on the Final Test Process Efficiency and Cost.

Hiromu Fujioka, Koji Nakamae, Akio Higashi

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996