Hiromitsu Kimura

According to our database1, Hiromitsu Kimura authored at least 20 papers between 1999 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2018
A 11.3-µA Physical Activity Monitoring System Using Acceleration and Heart Rate.
IEICE Trans. Electron., 2018

2017
A 19-μA metabolic equivalents monitoring SoC using adaptive sampling.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
A 15-μA metabolic equivalents monitoring system using adaptive acceleration sampling and normally off computing.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015
Normally Off ECG SoC With Non-Volatile MCU and Noise Tolerant Heartbeat Detector.
IEEE Trans. Biomed. Circuits Syst., 2015

A Wearable Healthcare System With a 13.7 µ A Noise Tolerant ECG Processor.
IEEE Trans. Biomed. Circuits Syst., 2015

A ferroelectric-based non-volatile flip-flop for wearable healthcare systems.
Proceedings of the 15th Non-Volatile Memory Technology Symposium, 2015

A low power 6T-4C non-volatile memory using charge sharing and non-precharge techniques.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
Highly Reliable Non-volatile Logic Circuit Technology and Its Application.
IEICE Trans. Inf. Syst., 2014

A 6.14µA normally-off ECG-SoC with noise tolerant heart rate extractor for wearable healthcare systems.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

A 2.4 pJ ferroelectric-based non-volatile flip-flop with 10-year data retention capability.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
A 38 μA wearable biosignal monitoring system with near field communication.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

A 14 µA ECG processor with robust heart rate monitor for a wearable healthcare system.
Proceedings of the ESSCIRC 2013, 2013

2007
Implementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor Logic.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2005
TMR-Based Logic-in-Memory Circuit for Low-Power VLSI.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

2004
Complementary ferroelectric-capacitor logic for low-power logic-in-memory VLSI.
IEEE J. Solid State Circuits, 2004

A Study of Multiple-Valued Magnetoresistive RAM (MRAM) Using Binary MTJ Devices.
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

2003
Multiple-Valued Logic-in-Memory VLSI Using MFSFETs and its Applications.
J. Multiple Valued Log. Soft Comput., 2003

2002
Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition.
Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002

2000
DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage.
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

1999
Multiple-Valued Content-Addressable Memory Using Metal-Ferroelectric-Semiconductor FETs.
Proceedings of the 29th IEEE International Symposium on Multiple-Valued Logic, 1999


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