Hiromi Inaba

According to our database, Hiromi Inaba authored at least 8 papers between 2012 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

25-Gb/s clock and data recovery IC using latch-load combined with CML buffer circuit for delay generation with 65-nm CMOS.

Tomonori Tanaka, Kosuke Furuichi, Hiromu Uemura, Ryosuke Noguchi, Natsuyuki Koda, Koki Arauchi, Daichi Omoto, Hiromi Inaba, Keiji Kishine, Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016

Proposal for sensitive frequency demodulator for 10-Gb/s transmission labeling signal system.

Natsuyuki Koda, Kosuke Furuichi, Hiromu Uemura, Hiromi Inaba, Keiji Kishine

Proceedings of the International SoC Design Conference, 2016

36-Gb/s CDR IC using simple passive loop filter combined with passive load in phase detector.

Keiji Kishine, Hiroshi Inoue, Kosuke Furuichi, Natsuyuki Koda, Hiromu Uemura, Hiromi Inaba, Makoto Nakamura, Akira Tsuchiya

Proceedings of the International SoC Design Conference, 2016

Design of high-linearity delay detection circuit for 10-Gb/s communication system in 65-nm CMOS.

Kosuke Furuichi, Hiromu Uemura, Natsuyuki Koda, Hiromi Inaba, Keiji Kishine

Proceedings of the International SoC Design Conference, 2016

2015

A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS.

Keiji Kishine, Hiromi Inaba, Hiroshi Inoue, Makoto Nakamura, Akira Tsuchiya, Hiroaki Katsurai, Hidetoshi Onodera

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

2014

A 65-nm CMOS burst-mode CDR based on a GVCO with symmetric loops.

Keiji Kishine, Hiroshi Inoue, Hiromi Inaba, Makoto Nakamura, Akira Tsuchiya, Hidetoshi Onodera, Hiroaki Katsurai

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

Analysis and design based on small-signal equivalent circuit for a lO-GHz ring VCO with 65-nm CMOS.

Keiji Kishine, Hiromi Inaba, Yusuke Ohtomo, Makoto Nakamura, Hiroshi Koizumi, Mitsuo Nakamura

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

2012

Design method for an over-IO-Gb/s CMOS CML buffer circuit for delay control.

Keiji Kishine, Hiromi Inaba, Yusuke Ohtomo, Makoto Nakamura, Mitsuo Nakamura

Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012