Hiroki Sunagawa

According to our database, Hiroki Sunagawa authored at least 4 papers between 2009 and 2011.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2011

Modeling of Random Telegraph Noise under circuit operation - Simulation and measurement of RTN-induced delay fluctuation.

Kyosuke Ito, Takashi Matsumoto, Shinichi Nishizawa, Hiroki Sunagawa, Kazutoshi Kobayashi, Hidetoshi Onodera

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

2010

Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells.

Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera

IPSJ Trans. Syst. LSI Des. Methodol., 2010

Variation-tolerant design of D-flipflops.

Hiroki Sunagawa, Hidetoshi Onodera

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

2009

Erect of regularity-enhanced layout on printability and circuit performance of standard cells.

Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009