Hiroki Sakurai
According to our database1,
Hiroki Sakurai
authored at least 8 papers
between 2005 and 2016.
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Bibliography
2016
An 18 µW spur canceled clock generator for recovering receiver sensitivity in wireless SoCs.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
2014
Gender-Dependent Babble Maskers Created from Multi-speaker Speech for Speech Privacy Protection.
Proceedings of the 2014 Tenth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, 2014
2012
A -70dBm-sensitivity 522Mbps 0.19nJ/bit-TX 0.43nJ/bit-RX transceiver for TransferJet™ SoC in 65nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012
2011
A 1.5GHz-modulation-range 10ms-modulation-period 180kHzrms-frequency-error 26MHz-reference mixed-mode FMCW synthesizer for mm-wave radar application.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2007
A Digitally Assisted Gain and Offset Error Cancellation Technique for a CMOS Pipelined ADC with a 1.5-bit Bit-Block Architecture.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
The Realization of an Area-Efficient CMOS Bandgap Reference Circuit with Less than 1.25 V of Output Voltage Using a Fractional <i>V<sub>BE</sub></i> Amplification Scheme.
IEICE Trans. Electron., 2007
A CMOS Current-mode DC-DC converter with input and output voltage-independent stability and frequency characteristics utilizing a quadratic slope compensation scheme.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
2005
Analysis and Design of a Current-Mode PWM Buck Converter Adopting the Output-Voltage Independent Second-Order Slope Compensation Scheme.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005