Hiroki Nakahara

According to our database, Hiroki Nakahara authored at least 107 papers between 2005 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

A Stacked FPGA utilizing 3D-SRAM with Latency Optimization.

Ryo Takahashi, Kota Ando, Hiroki Nakahara

Proceedings of the 17th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2024

A Weight Ternary Ensemble Vision Transformer Toward Memory Size Reduction.

Ryota Kayanoma, Hiroki Nakahara

Proceedings of the 54th IEEE International Symposium on Multiple-Valued Logic, 2024

2023

Remarn: A Reconfigurable Multi-threaded Multi-core Accelerator for Recurrent Neural Networks.

Zhiqiang Que, Hiroki Nakahara, Hongxiang Fan, He Li, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Eriko Nurvitadhi, Wayne Luk

ACM Trans. Reconfigurable Technol. Syst., March, 2023

A Many-core Architecture for an Ensemble Ternary Neural Network Toward High-Throughput Inference.

Ryota Kayanoma, Akira Jinguji, Hiroki Nakahara

Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

A Consideration on Ternary Adversarial Generative Networks.

Kennichi Nakamura, Hiroki Nakahara

Proceedings of the 53rd IEEE International Symposium on Multiple-Valued Logic, 2023

A Light-Weight Vision Transformer Toward Near Memory Computation on an FPGA.

Takeshi Senoo, Ryota Kayanoma, Akira Jinguji, Hiroki Nakahara

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2023

2022

Multilayer Perceptron Training Accelerator Using Systolic Array.

Takeshi Senoo, Akira Jinguji, Ryosuke Kuramochi, Hiroki Nakahara

IEICE Trans. Inf. Syst., December, 2022

Recurrent Neural Networks With Column-Wise Matrix-Vector Multiplication on FPGAs.

Zhiqiang Que, Hiroki Nakahara, Eriko Nurvitadhi, Andrew Boutros, Hongxiang Fan, Chenglong Zeng, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Wayne Luk

IEEE Trans. Very Large Scale Integr. Syst., 2022

Optimizations of Ternary Generative Adversarial Networks.

Kennichi Nakamura, Hiroki Nakahara

Proceedings of the 52nd IEEE International Symposium on Multiple-Valued Logic, 2022

Fast Interface with Ensemble Ternary Neural Network.

Ryota Kayanoma, Hiroki Nakahara

Proceedings of the 52nd IEEE International Symposium on Multiple-Valued Logic, 2022

Message from the General Chair and Program Co-Chairs.

Wei Zhang, Ray C. C. Cheung, Yun Liang, Hiroki Nakahara

Proceedings of the International Conference on Field-Programmable Technology, 2022

Preface.

Yun Liang, Hiroki Nakahara, Wei Zhang, Fubing Mao, Ray C. C. Cheung

Proceedings of the International Conference on Field-Programmable Technology, 2022

2021

FPGA-Based Inter-layer Pipelined Accelerators for Filter-Wise Weight-Balanced Sparse Fully Convolutional Networks with Overlapped Tiling.

Masayuki Shimoda, Youki Sada, Hiroki Nakahara

J. Signal Process. Syst., 2021

Energy-Efficient ECG Signals Outlier Detection Hardware Using a Sparse Robust Deep Autoencoder.

Naoto Soga, Shimpei Sato, Hiroki Nakahara

IEICE Trans. Inf. Syst., 2021

A Low-Latency Inference of Randomly Wired Convolutional Neural Networks on an FPGA.

Ryosuke Kuramochi, Hiroki Nakahara

IEICE Trans. Inf. Syst., 2021

Weight Sparseness for a Feature-Map-Split-CNN Toward Low-Cost Embedded FPGAs.

Akira Jinguji, Shimpei Sato, Hiroki Nakahara

IEICE Trans. Inf. Syst., 2021

A novel compact planar magic-T using CPS and microstrip-to-CPS transition.

Hiroki Nakahara, Takayuki Tanaka, Ichihiko Toyoda

IEICE Electron. Express, 2021

Detection of Wrong Direction Vehicles on Two-Way Traffic.

Pintusorn Suttiponpisarn, Chalermpol Charnsripinyo, Sasiporn Usanavasin, Hiroki Nakahara

Proceedings of the 13th International Conference on Knowledge and Systems Engineering, 2021

A High-Throughput Detection Circuit based on 2^q+1-Valued Deep Neural Networks.

Naoto Soga, Ryosuke Kuramochi, Hiroki Nakahara

Proceedings of the 51st IEEE International Symposium on Multiple-Valued Logic, 2021

Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner.

Kota Ando, Jaehoon Yu, Kazutoshi Hirose, Hiroki Nakahara, Kazushi Kawamura, Thiem Van Chu, Masato Motomura

Proceedings of the IEEE Hot Chips 33 Symposium, 2021

2020

SENTEI: Filter-Wise Pruning with Distillation towards Efficient Sparse Convolutional Neural Network Accelerators.

Masayuki Shimoda, Youki Sada, Ryosuke Kuramochi, Shimpei Sato, Hiroki Nakahara

IEICE Trans. Inf. Syst., 2020

A Table Look-Up Based Ternary Neural Network Processor.

Yuta Suzuki, Naoto Soga, Shimpei Sato, Hiroki Nakahara

Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020

2ⁿ+1-valued SSS-Net: Uniform Shift, Channel Sparseness, and Channel Shuffle.

Hiroki Nakahara

Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020

Fast Monocular Depth Estimation on an FPGA.

Youki Sada, Naoto Soga, Masayuki Shimoda, Akira Jinguji, Shimpei Sato, Hiroki Nakahara

Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020

Design Method for an LUT Network-Based CNN with a Sparse Local Convolution.

Naoto Soga, Hiroki Nakahara

Proceedings of the International Conference on Field-Programmable Technology, 2020

A Reconfigurable Multithreaded Accelerator for Recurrent Neural Networks.

Zhiqiang Que, Hiroki Nakahara, Hongxiang Fan, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Eriko Nurvitadhi, Wayne Luk

Proceedings of the International Conference on Field-Programmable Technology, 2020

An FPGA-Based Low-Latency Accelerator for Randomly Wired Neural Networks.

Ryosuke Kuramochi, Hiroki Nakahara

Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

R2CNN: Recurrent Residual Convolutional Neural Network on FPGA.

Hiroki Nakahara, Zhiqiang Que, Akira Jinguji, Wayne Luk

Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

Optimizing Reconfigurable Recurrent Neural Networks.

Zhiqiang Que, Hiroki Nakahara, Eriko Nurvitadhi, Hongxiang Fan, Chenglong Zeng, Jiuxi Meng, Xinyu Niu, Wayne Luk

Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

High-Throughput Convolutional Neural Network on an FPGA by Customized JPEG Compression.

Hiroki Nakahara, Zhiqiang Que, Wayne Luk

Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

Tiny On-Chip Memory Realization of Weight Sparseness Split-CNNs on Low-end FPGAs.

Akira Jinguji, Shimpei Sato, Hiroki Nakahara

Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

2019

Power Efficient Object Detector with an Event-Driven Camera for Moving Object Surveillance on an FPGA.

Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara

IEICE Trans. Inf. Syst., 2019

GUINNESS: A GUI Based Binarized Deep Neural Network Framework for Software Programmers.

Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda, Shimpei Sato

IEICE Trans. Inf. Syst., 2019

FPGA-based Accurate Pedestrian Detection with Thermal Camera for Surveillance System.

Ryosuke Kuramochi, Masayuki Shimoda, Youki Sada, Shimpei Sato, Hiroki Nakahara

Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019

Many Universal Convolution Cores for Ensemble Sparse Convolutional Neural Networks.

Ryosuke Kuramochi, Youki Sada, Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara

Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

Noise Convolutional Neural Networks and FPGA Implementation.

Atsuki Munakata, Hiroki Nakahara, Shimpei Sato

Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019

A Dataflow Pipelining Architecture for Tile Segmentation with a Sparse MobileNet on an FPGA.

Youki Sada, Masayuki Shimoda, Akira Jinguji, Hiroki Nakahara

Proceedings of the International Conference on Field-Programmable Technology, 2019

An FPGA Implementation of Real-Time Object Detection with a Thermal Camera.

Masayuki Shimoda, Youki Sada, Ryosuke Kuramochi, Hiroki Nakahara

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

FPGA-Based Training Accelerator Utilizing Sparseness of Convolutional Neural Network.

Hiroki Nakahara, Youki Sada, Masayuki Shimoda, Kouki Sayama, Akira Jinguji, Shimpei Sato

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

Real-Time Multi-Pedestrian Detection in Surveillance Camera using FPGA.

Akira Jinguji, Youki Sada, Hiroki Nakahara

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

An FPGA-based Fine Tuning Accelerator for a Sparse CNN.

Hiroki Nakahara, Akira Jinguji, Masayuki Shimoda, Shimpei Sato

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Filter-Wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation.

Masayuki Shimoda, Youki Sada, Hiroki Nakahara

Proceedings of the Applied Reconfigurable Computing - 15th International Symposium, 2019

2018

BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W.

Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura

IEEE J. Solid State Circuits, 2018

An FPGA Realization of a Random Forest with <i>k</i>-Means Clustering Using a High-Level Synthesis Design.

Akira Jinguji, Shimpei Sato, Hiroki Nakahara

IEICE Trans. Inf. Syst., 2018

A Threshold Neuron Pruning for a Binarized Deep Neural Network on an FPGA.

Tomoya Fujii, Shimpei Sato, Hiroki Nakahara

IEICE Trans. Inf. Syst., 2018

New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications.

Taro Fujii, Takao Toi, Teruhito Tanaka, Katsumi Togawa, Toshiro Kitaoka, Kengo Nishino, Noritsugu Nakamura, Hiroki Nakahara, Masato Motomura

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A Ternary Weight Binary Input Convolutional Neural Network: Realization on the Embedded Processor.

Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara

Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

A High-speed Low-power Deep Neural Network on an FPGA based on the Nested RNS: Applied to an Object Detector.

Hiroki Nakahara, Tsutomu Sasao

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Power Efficient Object Detector with an Event-Driven Camera on an FPGA.

Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara

Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2018

A Performance Per Power Efficient Object Detector on an FPGA for Robot Operating System (ROS).

Haoxuan Cheng, Shimpei Sato, Hiroki Nakahara

Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2018

A Tri-State Weight Convolutional Neural Network for an FPGA: Applied to YOLOv2 Object Detector.

Hiroki Nakahara, Masayuki Shimoda, Shimpei Sato

Proceedings of the International Conference on Field-Programmable Technology, 2018

An FPGA Realization of OpenPose Based on a Sparse Weight Convolutional Neural Network.

Akira Jinguji, Tomoya Fujii, Shimpei Sato, Hiroki Nakahara

Proceedings of the International Conference on Field-Programmable Technology, 2018

Demonstration of Object Detection for Event-Driven Cameras on FPGAs and GPUs.

Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

A Demonstration of FPGA-Based You Only Look Once Version2 (YOLOv2).

Hiroki Nakahara, Masayuki Shimoda, Shimpei Sato

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

A Lightweight YOLOv2: A Binarized CNN with A Parallel Support Vector Regression for an FPGA.

Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Shimpei Sato

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

Hardware Algorithms.

Kentaro Sano, Hiroki Nakahara

Proceedings of the Principles and Structures of FPGAs., 2018

2017

In-memory area-efficient signal streaming processor design for binary neural networks.

Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Kota Ando, Kodai Ueyoshi, Kazutoshi Hirose, Kentaro Orimo, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A Random Forest Using a Multi-valued Decision Diagram on an FPGA.

Hiroki Nakahara, Akira Jinguji, Simpei Sato, Tsutomu Sasao

Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017

On-Chip Memory Based Binarized Convolutional Deep Neural Network Applying Batch Normalization Free Technique on an FPGA.

Haruyoshi Yonekawa, Hiroki Nakahara

Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

All binarized convolutional neural network and its implementation on an FPGA.

Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara

Proceedings of the International Conference on Field Programmable Technology, 2017

An object detector based on multiscale sliding window search using a fully pipelined binarized CNN on an FPGA.

Hiroki Nakahara, Haruyoshi Yonekawa, Shimpei Sato

Proceedings of the International Conference on Field Programmable Technology, 2017

A fully connected layer elimination for a binarizec convolutional neural network on an FPGA.

Hiroki Nakahara, Tomoya Fujii, Shimpei Sato

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA (Abstract Only).

Hiroki Nakahara, Haruyoshi Yonekawa, Hisashi Iwamoto, Masato Motomura

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

An FPGA Realization of a Deep Convolutional Neural Network Using a Threshold Neuron Pruning.

Tomoya Fujii, Simpei Sato, Hiroki Nakahara, Masato Motomura

Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017

2016

An FFT Circuit for a Spectrometer of a Radio Telescope using the Nested RNS including the Constant Division.

Hiroki Nakahara, Hiroyuki Nakanishi, Kazumasa Iwai, Tsutomu Sasao

SIGARCH Comput. Archit. News, 2016

An Update Method for a Low Power Cam Emulator Using an LUT Cascade Based on an EVMDD (<i>k</i>).

Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Hisashi Iwamoto

J. Multiple Valued Log. Soft Comput., 2016

LUT Cascades Based on Edge-Valued Multi-Valued Decision Diagrams: Application to Packet Classification.

Hiroki Nakahara, Tsutomu Sasao, Hisashi Iwamoto, Munehiro Matsuura

IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

An FFT Circuit Using Nested RNS in a Digital Spectrometer for a Radio Telescope.

Hiroki Nakahara, Tsutomu Sasao, Hiroyuki Nakanishi, Kazumasa Iwai, Tohru Nagao, Naoya Ogawa

Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

A memory-based realization of a binarized deep convolutional neural network.

Hiroki Nakahara, Haruyoshi Yonekawa, Tsutomu Sasao, Hisashi Iwamoto, Masato Motomura

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

An acceleration of a random forest classification using Altera SDK for OpenCL.

Hiroki Nakahara, Akira Jinguji, Tomonori Fujii, Simpei Sato

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

2015

A Memory-Based IPv6 Lookup Architecture Using Parallel Index Generation Units.

Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Hisashi Iwamoto, Yasuhiro Terao

IEICE Trans. Inf. Syst., 2015

An RNS FFT Circuit Using LUT Cascades Based on a Modulo EVMDD.

Hiroki Nakahara, Tsutomu Sasao, Hiroyuki Nakanishi, Kazumasa Iwai

Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

A deep convolutional neural network based on nested residue number system.

Hiroki Nakahara, Tsutomu Sasao

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

A Dynamically Reconfigurable Mixed Analog-Digital Filter Bank.

Hiroki Nakahara, Hideki Yoshida, Shin-ich Shioya, Renji Mikami, Tsutomu Sasao

Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014

A Heterogeneous Multi-valued Decision Diagram Machine for Encoded Characteristic Function for Non-zero Outputs.

Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura

J. Multiple Valued Log. Soft Comput., 2014

A Packet Classifier Based on Prefetching EVMDD (<i>k</i>) Machines.

Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura

IEICE Trans. Inf. Syst., 2014

An AWF digital spectrometer for a radio telescope.

Hiroki Nakahara, Hiroyuki Nakanishi, Kazumasa Iwai

Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

An Update Method for a CAM Emulator Using an LUT Cascade Based on an EVMDD (K).

Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura

Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

Automatic adjustment system for optical interconnection transmitter using improved particle swarm optimization.

Kenichi Ohhata, Hiroki Nakahara, Takuya Inoue, Toru Yazaki, Norio Chujo, Takuma Nishimoto

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

2013

A Virus Scanning Engine Using an MPU and an IGU Based on Row-Shift Decomposition.

Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura

IEICE Trans. Inf. Syst., 2013

A Machine to Evaluate Decomposed Multi-Terminal Multi-Valued Decision Diagrams for Characteristic Functions.

Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura

Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013

A high-speed FFT based on a six-step algorithm: Applied to a radio telescope for a solar radio burst.

Hiroki Nakahara, Kazumasa Iwai, Hiroyuki Nakanishi

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

A packet classifier using LUT cascades based on EVMDDS (k).

Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

An Architecture for IPv6 Lookup Using Parallel Index Generation Units.

Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

2012

On a wideband fast fourier transform for a radio telescope.

Hiroki Nakahara, Hiroyuki Nakanishi, Tsutomu Sasao

SIGARCH Comput. Archit. News, 2012

A Comparison of Multi-Valued and Heterogeneous Decision Diagram Machines.

Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura

J. Multiple Valued Log. Soft Comput., 2012

A regular expression matching circuit: Decomposed non-deterministic realization with prefix sharing and multi-character transition.

Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura

Microprocess. Microsystems, 2012

A Design Method of a Regular Expression Matching Circuit Based on Decomposed Automaton.

Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura

IEICE Trans. Inf. Syst., 2012

Multi-terminal Multi-valued Decision Diagrams for Characteristic Function Representing Cluster Decomposition.

Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura

Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

On a Wideband Fast Fourier Transform Using Piecewise Linear Approximations: Application to a Radio Telescope Spectrometer.

Hiroki Nakahara, Hiroyuki Nakanishi, Tsutomu Sasao

Proceedings of the Algorithms and Architectures for Parallel Processing, 2012

A Low-Cost and High-Performance Virus Scanning Engine Using a Binary CAM Emulator and an MPU.

Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011

A Comparison of Heterogeneous Multi-valued Decision Diagram Machines for Multiple-Output Logic Functions.

Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura

Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011

A Regular Expression Matching Circuit Based on a Decomposed Automaton.

Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2010

A Quaternary Decision Diagram Machine: Optimization of Its Code.

Tsutomu Sasao, Hiroki Nakahara, Munehiro Matsuura, Yoshifumi Kawamura, Jon T. Butler

IEICE Trans. Inf. Syst., 2010

A Parallel Branching Program Machine for Sequential Circuits: Implementation and Evaluation.

Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura

IEICE Trans. Inf. Syst., 2010

A Comparison of Architectures for Various Decision Diagram Machines.

Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura

Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic, 2010

A Packet Classifier Using a Parallel Branching Program Machine.

Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009

A Quaternary Decision Diagram Machine and the Optimization of its Code.

Tsutomu Sasao, Hiroki Nakahara, Munehiro Matsuura, Yoshifumi Kawamura, Jon T. Butler

Proceedings of the ISMVL 2009, 2009

A virus scanning engine using a parallel finite-input memory machine and MPUs.

Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

The Parallel Sieve Method for a Virus Scanning Engine.

Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

A Parallel Branching Program Machine for Emulation of Sequential Circuits.

Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura

Proceedings of the Reconfigurable Computing: Architectures, 2009

2007

A CAM Emulator Using Look-Up Table Cascades.

Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura

Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Implementations of Reconfigurable Logic Arrays on FPGAs.

Tsutomu Sasao, Hiroki Nakahara

Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

2006

A PC-Based Logic Simulator Using a Look-Up Table Cascade Emulator.

Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

A Soft Error Tolerant LUT Cascade Emulator.

Hiroki Nakahara, Tsutomu Sasao

Proceedings of the 15th Asian Test Symposium, 2006

A fast logic simulator using a look up table cascade emulator.

Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

A Design Algorithm for Sequential Circuits Using LUT Rings.

Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005