Hiroki Koike

According to our database1, Hiroki Koike authored at least 22 papers between 1990 and 2022.

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Bibliography

2022
Design and Heavy-Ion Testing of MTJ/CMOS Hybrid LSIs for Space-Grade Soft-Error Reliability.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

2019
A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications.
IEEE J. Solid State Circuits, 2019

Cyclic groups are CI-groups for balanced configurations.
Des. Codes Cryptogr., 2019

A novel memory test system with an electromagnet for STT-MRAM testing.
Proceedings of the 19th Non-Volatile Memory Technology Symposium, 2019

An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
Accurate error bit mode analysis of STT-MRAM chip with a novel current measurement module implemented to gigabit class memory test system.
Proceedings of the Non-Volatile Memory Technology Symposium, 2018

2017
Flag Bicolorings, Pseudo-Orientations, and Double Covers of Maps.
Electron. J. Comb., 2017

2016
Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing.
Proc. IEEE, 2016

An Overview of Nonvolatile Emerging Memories - Spintronics for Working Memories.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2014
Isomorphic tetravalent cyclic Haar graphs.
Ars Math. Contemp., 2014

2013
A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme.
IEEE J. Solid State Circuits, June, 2013

2012
1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times.
Proceedings of the Symposium on VLSI Circuits, 2012

High-speed simulator including accurate MTJ models for spintronics integrated circuit design.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
An Electrically Adjustable 3-Terminal Regulator for Post-Fabrication Level-Trimming with a Reliable 1-Wire Serial I/O.
IEICE Trans. Electron., 2011

2010
An electrically adjustable 3-terminal regulator with post-fabrication level-trimming function.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2002
A 128-kb FeRAM macro for contact/contactless smart-card microcontrollers.
IEEE J. Solid State Circuits, 2002

2001
NV-SRAM: a nonvolatile SRAM with backup ferroelectric capacitors.
IEEE J. Solid State Circuits, 2001

FeRAM device and circuit technologies fully compatible with advanced CMOS.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

2000
NV-SRAM: a nonvolatile SRAM with back-up ferroelectric capacitors.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1998
An embedded FeRAM macro cell for a smart card microcontroller.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

1990
A BIST scheme using microprogram ROM for large capacity memories.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990


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