Hiroki Kihara

According to our database1, Hiroki Kihara authored at least 2 papers between 1993 and 2010.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

1994
1996
1998
2000
2002
2004
2006
2008
2010
0
1
2
1
1

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2010
A 1.296-to-5.184Gb/s Transceiver with 2.4mW/(Gb/s) Burst-mode CDR using Dual-Edge Injection-Locked Oscillator.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

1993
A 9-ns 16-Mb CMOS SRAM with offset-compensated current sense amplifier.
IEEE J. Solid State Circuits, November, 1993


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