Hiroki Fujisawa

According to our database, Hiroki Fujisawa authored at least 8 papers between 1997 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2007

An 8.1-ns Column-Access 1.6-Gb/s/pin DDR3 SDRAM With an 8: 4 Multiplexed Data-Transfer Scheme.

Hiroki Fujisawa, Shuichi Kubouchi, Koji Kuroki, Naohisa Nishioka, Yoshiro Riho, Hiromasa Noda, Isamu Fujii, Hideyuki Yoko, Ryuuji Takishita, Takahiro Ito, Hitoshi Tanaka, Masayuki Nakamura

IEEE J. Solid State Circuits, 2007

2006

An 8.4ns Column-Access 1.3Gb/s/pin DDR3 SDRAM with an 8: 4 Multiplexed Data-Transfer Scheme.

Hiroki Fujisawa, Shuichi Kubouchi, Koji Kuroki, Naohisa Nishioka, Yoshiro Riho, Hiromasa Noda, Isamu Fujii, Hideyuki Yoko, Ryuuji Takishita, Takahiro Ito, Hitoshi Tanaka, Masayuki Nakamura

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005

1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer.

Hiroki Fujisawa, Masayuki Nakamura, Yasuhiro Takai, Yasuji Koshikawa, Tatsuya Matano, Seiji Narui, Narikazu Usuki, Chiaki Dono, Shinichi Miyatake, Makoto Morino, Koji Arai, Shuichi Kubouchi, Isamu Fujii, Hideyuki Yoko, Takao Adachi

IEEE J. Solid State Circuits, 2005

2003

A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer.

Tatsuya Matano, Yasuhiro Takai, Tsugio Takahashi, Yuusuke Sakito, Isamu Fujii, Yoshihiro Takaishi, Hiroki Fujisawa, Shuichi Kubouchi, Seiji Narui, Koji Arai, Makoto Morino, Masayuki Nakamura, Shinichi Miyatake, Toshihiro Sekiguchi, Kuniaki Koyama

IEEE J. Solid State Circuits, 2003

2002

A low-impedance open-bitline array for multigigabit DRAM.

Tomonori Sekiguchi, Kiyoo Itoh, Tsugio Takahashi, Masahiro Sugaya, Hiroki Fujisawa, Masayuki Nakamura, Kazuhiko Kajigaya, Katsutaka Kimura

IEEE J. Solid State Circuits, 2002

2001

A multigigabit DRAM technology with 6F² open-bitline cell, distributed overdriven sensing, and stacked-flash fuse.

Tsugio Takahashi, Tomonori Sekiguchi, Riichiro Takemura, Seiji Narui, Hiroki Fujisawa, Shinichi Miyatake, Makoto Morino, Koji Arai, Satoru Yamada, Shoji Shukuri, Masayuki Nakamura, Yoshitaka Tadaki, Kazuhiko Kajigaya, Katsutaka Kimura, Kiyoo Itoh

IEEE J. Solid State Circuits, 2001

A dual-phase-controlled dynamic latched amplifier for high-speed and low-power DRAMs.

Hiroki Fujisawa, Tsugio Takahashi, Masayuki Nakamura, Kazuhiko Kajigaya

IEEE J. Solid State Circuits, 2001

1997

The charge-share modified (CSM) precharge-level architecture for high-speed and low-power ferroelectric memory.

Hiroki Fujisawa, Takeshi Sakata, Tomonori Sekiguchi, Osamu Nagashima, Katsutaka Kimura, Kazuhiko Kajigaya

IEEE J. Solid State Circuits, 1997