Hirokatsu Shirahama
According to our database1,
Hirokatsu Shirahama
authored at least 12 papers
between 2006 and 2014.
Collaborative distances:
Collaborative distances:
Timeline
2006
2007
2008
2009
2010
2011
2012
2013
2014
0
1
2
3
4
5
6
2
1
1
1
3
1
1
1
1
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2014
High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs.
IEICE Trans. Inf. Syst., 2014
Design of an Energy-Efficient Ternary Current-Mode Intra-Chip Communication Link for an Asynchronous Network-on-Chip.
IEICE Trans. Inf. Syst., 2014
Design of a Quaternary Single-Ended Current-Mode Circuit for an Energy-Efficient Inter-chip Asynchronous Communication Link.
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Highly reliable single-ended current-mode circuit for an inter-chip asynchronous communication link.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
2010
Energy-Aware Multiple-Valued Current-Mode Sequential Circuits Using a Completion-Detection Scheme.
IEICE Trans. Inf. Syst., 2010
2009
Timing-Variation-Aware Multiple-Valued Current-Mode Circuit for a Low-Power Pipelined System.
Proceedings of the ISMVL 2009, 2009
2008
Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008
2007
Design and Evaluation of a 54 x 54-bit Multiplier Based on Differential-Pair Circuitry.
IEICE Trans. Electron., 2007
Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor.
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007
2006
IEICE Trans. Electron., 2006
Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006